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[Qemu-devel] [PATCH 16/16] exec-all.h: Increase MAX_OP_PER_INSTR for ARM
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 16/16] exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder |
Date: |
Sun, 9 Mar 2014 15:11:07 +0000 |
The ARM A64 decoder's worst case number of TCG ops per instruction
is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures
store). Raise the MAX_OP_PER_INSTR define accordingly.
Signed-off-by: Peter Maydell <address@hidden>
---
include/exec/exec-all.h | 2 +-
target-arm/translate-a64.c | 12 ++++++++++--
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index a387922..6af84f6 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -44,7 +44,7 @@ struct TranslationBlock;
typedef struct TranslationBlock TranslationBlock;
/* XXX: make safe guess about sizes */
-#define MAX_OP_PER_INSTR 208
+#define MAX_OP_PER_INSTR 266
#if HOST_LONG_BITS == 32
#define MAX_OPC_PARAM_PER_ARG 2
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 6a3597d..2435c95 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -9007,9 +9007,8 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
case 0x19: /* FRINTM */
case 0x38: /* FRINTP */
case 0x39: /* FRINTZ */
- case 0x58: /* FRINTA */
need_rmode = true;
- rmode = extract32(opcode, 5, 2) | (extract32(opcode, 0, 1) << 1);
+ rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
/* fall through */
case 0x59: /* FRINTX */
case 0x79: /* FRINTI */
@@ -9019,6 +9018,15 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
return;
}
break;
+ case 0x58: /* FRINTA */
+ need_rmode = true;
+ rmode = FPROUNDING_TIEAWAY;
+ need_fpstatus = true;
+ if (size == 3 && !is_q) {
+ unallocated_encoding(s);
+ return;
+ }
+ break;
case 0x3c: /* URECPE */
case 0x3d: /* FRECPE */
case 0x56: /* FCVTXN, FCVTXN2 */
--
1.9.0
- [Qemu-devel] [PATCH 04/16] target-arm: A64: Add FSQRT to C3.6.17 (two misc), (continued)
- [Qemu-devel] [PATCH 04/16] target-arm: A64: Add FSQRT to C3.6.17 (two misc), Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 07/16] target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 08/16] target-arm: A64: Implement SHLL, SHLL2, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 09/16] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 13/16] target-arm: A64: Add FRECPX (reciprocal exponent), Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 05/16] target-arm: A64: Add remaining CLS/Z vector ops, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 03/16] target-arm: A64: Add last AdvSIMD Integer to FP ops, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 15/16] target-arm: A64: Implement FRINT*, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 01/16] target-arm: A64: Implement PMULL instruction, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 16/16] exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder,
Peter Maydell <=
- [Qemu-devel] [PATCH 14/16] target-arm: A64: Implement SRI, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 06/16] target-arm: A64: Saturating and narrowing shift ops, Peter Maydell, 2014/03/09