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[Qemu-devel] [PULL 123/130] target-ppc: Use Additional Temporary in stqc
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 123/130] target-ppc: Use Additional Temporary in stqcx Case |
Date: |
Fri, 7 Mar 2014 00:34:10 +0100 |
From: Tom Musta <address@hidden>
Per Alex Graf's suggestion, the recently added case to gen_conditional_store
for stqcx should use an additional temporary when accessing the second
doubleword. This avoids the mutation of the EA argument to the function,
which is counter intuitive.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/translate.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 051693b..91c33dc 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3333,7 +3333,7 @@ static void gen_conditional_store(DisasContext *ctx, TCGv
EA,
gen_qemu_st16(ctx, cpu_gpr[reg], EA);
#if defined(TARGET_PPC64)
} else if (size == 16) {
- TCGv gpr1, gpr2;
+ TCGv gpr1, gpr2 , EA8;
if (unlikely(ctx->le_mode)) {
gpr1 = cpu_gpr[reg+1];
gpr2 = cpu_gpr[reg];
@@ -3342,8 +3342,10 @@ static void gen_conditional_store(DisasContext *ctx,
TCGv EA,
gpr2 = cpu_gpr[reg+1];
}
gen_qemu_st64(ctx, gpr1, EA);
- gen_addr_add(ctx, EA, EA, 8);
- gen_qemu_st64(ctx, gpr2, EA);
+ EA8 = tcg_temp_local_new();
+ gen_addr_add(ctx, EA8, EA, 8);
+ gen_qemu_st64(ctx, gpr2, EA8);
+ tcg_temp_free(EA8);
#endif
} else {
gen_qemu_st8(ctx, cpu_gpr[reg], EA);
--
1.8.1.4
- [Qemu-devel] [PULL 114/130] target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum, (continued)
- [Qemu-devel] [PULL 114/130] target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 118/130] target-ppc: Altivec 2.07: Vector Permute and Exclusive OR, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 119/130] spapr-vlan: flush queue whenever can_receive can go from false to true, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 115/130] target-ppc: Altivec 2.07: Binary Coded Decimal Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 117/130] target-ppc: Altivec 2.07: Vector SHA Sigma Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 113/130] target-ppc: Altivec 2.07: Vector Gather Bits by Bytes, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 116/130] target-ppc: Altivec 2.07: AES Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 089/130] target-ppc: Add Load Quadword and Reserve, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 121/130] PPC: sPAPR: Only use getpagesize() when we run with kvm, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 124/130] target-ppc: Fix htab_mask calculation, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 123/130] target-ppc: Use Additional Temporary in stqcx Case,
Alexander Graf <=
- [Qemu-devel] [PULL 130/130] target-ppc: spapr: e500: fix to use cpu_dt_id, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 128/130] target-ppc: Introduce hypervisor call H_GET_TCE, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 122/130] target-ppc: Fix Compiler Warnings Due to 64-Bit Constants Declared as UL, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 129/130] target-ppc: add PowerPCCPU::cpu_dt_id, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 125/130] target-ppc: Fix page table lookup with kvm enabled, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 127/130] target-ppc: Update ppc_hash64_store_hpte to support updating in-kernel htab, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 126/130] target-ppc: Change the hpte store API, Alexander Graf, 2014/03/06