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[Qemu-devel] [PULL 07/45] target-arm: Load correct access bits from ARMv
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 07/45] target-arm: Load correct access bits from ARMv5 level 2 page table descriptors |
Date: |
Wed, 26 Feb 2014 18:01:57 +0000 |
In ARMv5 level 2 page table descriptors, each 4K or 64K page is split into
four subpages, each of which can have different access permission settings,
which are specified by four two-bit fields in the l2 descriptor. A
long-standing cut-and-paste error meant we were using the wrong bits in
the virtual address to select the access-permission field for 4K pages.
The error has presumably not been noticed before because most guests don't
make use of the ability to set the access permissions differently for
each 1K subpage: if the guest gives the whole page the same access
permissions it doesn't matter which of the 4 AP fields we select.
(The whole issue is irrelevant for ARMv7 CPUs anyway because subpages
aren't supported there.)
Reported-by: Vivek Rai <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c993581..b44aa1b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2798,7 +2798,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t
address, int access_type,
break;
case 2: /* 4k page. */
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
- ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
+ ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
*page_size = 0x1000;
break;
case 3: /* 1k page. */
--
1.9.0
- [Qemu-devel] [PULL 26/45] target-arm: Implement AArch64 MPIDR, (continued)
- [Qemu-devel] [PULL 26/45] target-arm: Implement AArch64 MPIDR, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 08/45] hw/intc/arm_gic: Fix GIC_SET_LEVEL, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 32/45] target-arm: A64: Implement WFI, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 19/45] target-arm: Implement AArch64 TLB invalidate ops, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 02/45] hw/net/stellaris_enet: Avoid unintended sign extension, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 01/45] hw/misc/arm_sysctl: Fix bad boundary check on mb clock accesses, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 09/45] linux-headers: Update from v3.14-rc3, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 21/45] target-arm: Implement AArch64 memory attribute registers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 18/45] target-arm: Implement AArch64 cache invalidate/clean ops, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 03/45] hw/timer/arm_timer: Avoid array overrun for bad addresses, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 07/45] target-arm: Load correct access bits from ARMv5 level 2 page table descriptors,
Peter Maydell <=
- [Qemu-devel] [PULL 06/45] hw/arm/musicpal: Remove nonexistent CDTP2, CDTP3 registers, Peter Maydell, 2014/02/26
- Re: [Qemu-devel] [PULL 00/45] target-arm queue, Peter Maydell, 2014/02/27