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[Qemu-devel] [PULL 01/30] hw/intc/arm_gic: Fix NVIC assertion failure
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/30] hw/intc/arm_gic: Fix NVIC assertion failure |
Date: |
Thu, 20 Feb 2014 11:17:05 +0000 |
Commit 40d225009ef accidentally changed the behaviour of
gic_acknowledge_irq() for the NVIC. The NVIC doesn't have SGIs,
so this meant we hit an assertion:
gic_acknowledge_irq: Assertion `s->sgi_pending[irq][cpu] != 0' failed.
Return NVIC acknowledge-irq to its previous behaviour, like 11MPCore.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Christoffer Dall <address@hidden>
---
hw/intc/arm_gic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 93eaa6b..955b8d4 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -189,7 +189,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu)
}
s->last_active[irq][cpu] = s->running_irq[cpu];
- if (s->revision == REV_11MPCORE) {
+ if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
/* Clear pending flags for both level and edge triggered interrupts.
* Level triggered IRQs will be reasserted once they become inactive.
*/
--
1.8.5
- [Qemu-devel] [PULL 07/30] target-arm: A64: Implement floating point pairwise insns, (continued)
- [Qemu-devel] [PULL 07/30] target-arm: A64: Implement floating point pairwise insns, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 26/30] target-arm: A64: Add most remaining three-reg-diff widening ops, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 25/30] target-arm: A64: Add opcode comments to disas_simd_three_reg_diff, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 24/30] target-arm: A64: Implement store-exclusive for system mode, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 23/30] target-arm: Fix incorrect type for value argument to write_raw_cp_reg, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 22/30] target-arm: Remove failure status return from read/write_raw_cp_reg, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 20/30] target-arm: Drop success/fail return from cpreg read and write functions, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 21/30] target-arm: Remove unnecessary code now read/write fns can't fail, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 19/30] target-arm: Convert miscellaneous reginfo structs to accessfn, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 08/30] softfloat: Support halving the result of muladd operation, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 01/30] hw/intc/arm_gic: Fix NVIC assertion failure,
Peter Maydell <=
- [Qemu-devel] [PULL 04/30] target-arm: A64: Implement SIMD scalar indexed instructions, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 02/30] target-arm: A64: Implement plain vector SIMD indexed element insns, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 14/30] target-arm: Log bad system register accesses with LOG_UNIMP, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 17/30] target-arm: Convert performance monitor reginfo to accessfn, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 15/30] target-arm: Stop underdecoding ARM946 PRBS registers, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 12/30] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 18/30] target-arm: Convert generic timer reginfo to accessfn, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 11/30] target-arm: Define names for SCTLR bits, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 03/30] target-arm: A64: Implement long vector x indexed insns, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 13/30] target-arm: Remove unused ARMCPUState sr substruct, Peter Maydell, 2014/02/20