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[Qemu-devel] [PULL 00/30] target-arm queue
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 00/30] target-arm queue |
Date: |
Thu, 20 Feb 2014 11:17:04 +0000 |
Here's the latest target-arm pull request. There are definitely
more things still in the pipeline so there will be at least one
more before softfreeze...
thanks
-- PMM
The following changes since commit 46eef33b89e936ca793e13c4aeea1414e97e8dbb:
Fix QEMU build on OpenBSD on x86 archs (2014-02-17 11:44:00 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20140220
for you to fetch changes up to 2ea5a2ca1f1dc302652d2ad5035e0b209ccaa177:
linux-user: AArch64: Fix exclusive store of the zero register (2014-02-20
10:35:56 +0000)
----------------------------------------------------------------
target-arm queue:
* Fix a bug causing an assertion in the NVIC on ARMv7M models
* More A64 Neon instructions
* Refactor cpreg API to separate out access check functions, as
groundwork for AArch64 system mode
* Fix bug in linux-user A64 store-exclusive of XZR
----------------------------------------------------------------
Alex Bennée (2):
target-arm: A64: Implement SIMD FP compare and set insns
target-arm: A64: Implement floating point pairwise insns
Janne Grunau (1):
linux-user: AArch64: Fix exclusive store of the zero register
Peter Maydell (27):
hw/intc/arm_gic: Fix NVIC assertion failure
target-arm: A64: Implement plain vector SIMD indexed element insns
target-arm: A64: Implement long vector x indexed insns
target-arm: A64: Implement SIMD scalar indexed instructions
target-arm: A64: Implement scalar three different instructions
softfloat: Support halving the result of muladd operation
target-arm: A64: Implement remaining 3-same instructions
target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs
target-arm: Define names for SCTLR bits
target-arm: Restrict check_ap() use of S and R bits to v6 and earlier
target-arm: Remove unused ARMCPUState sr substruct
target-arm: Log bad system register accesses with LOG_UNIMP
target-arm: Stop underdecoding ARM946 PRBS registers
target-arm: Split cpreg access checks out from read/write functions
target-arm: Convert performance monitor reginfo to accessfn
target-arm: Convert generic timer reginfo to accessfn
target-arm: Convert miscellaneous reginfo structs to accessfn
target-arm: Drop success/fail return from cpreg read and write functions
target-arm: Remove unnecessary code now read/write fns can't fail
target-arm: Remove failure status return from read/write_raw_cp_reg
target-arm: Fix incorrect type for value argument to write_raw_cp_reg
target-arm: A64: Implement store-exclusive for system mode
target-arm: A64: Add opcode comments to disas_simd_three_reg_diff
target-arm: A64: Add most remaining three-reg-diff widening ops
target-arm: A64: Implement the wide 3-reg-different operations
target-arm: A64: Implement narrowing three-reg-diff operations
target-arm: A64: Implement unprivileged load/store
fpu/softfloat.c | 38 ++
hw/arm/pxa2xx.c | 36 +-
hw/arm/pxa2xx_pic.c | 11 +-
hw/intc/arm_gic.c | 2 +-
include/fpu/softfloat.h | 3 +
linux-user/main.c | 6 +-
target-arm/cpu.c | 8 +-
target-arm/cpu.h | 105 +++-
target-arm/helper-a64.c | 105 ++++
target-arm/helper-a64.h | 9 +
target-arm/helper.c | 620 +++++++++-----------
target-arm/helper.h | 3 +
target-arm/kvm-consts.h | 16 +-
target-arm/neon_helper.c | 16 +
target-arm/op_helper.c | 46 +-
target-arm/translate-a64.c | 1358 ++++++++++++++++++++++++++++++++++++++------
target-arm/translate.c | 28 +-
17 files changed, 1815 insertions(+), 595 deletions(-)
- [Qemu-devel] [PULL 00/30] target-arm queue,
Peter Maydell <=
- [Qemu-devel] [PULL 10/30] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 09/30] target-arm: A64: Implement remaining 3-same instructions, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 16/30] target-arm: Split cpreg access checks out from read/write functions, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 30/30] linux-user: AArch64: Fix exclusive store of the zero register, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 29/30] target-arm: A64: Implement unprivileged load/store, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 28/30] target-arm: A64: Implement narrowing three-reg-diff operations, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 27/30] target-arm: A64: Implement the wide 3-reg-different operations, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 07/30] target-arm: A64: Implement floating point pairwise insns, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 26/30] target-arm: A64: Add most remaining three-reg-diff widening ops, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 25/30] target-arm: A64: Add opcode comments to disas_simd_three_reg_diff, Peter Maydell, 2014/02/20