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Re: [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear beha
From: |
Beniamino Galvani |
Subject: |
Re: [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour |
Date: |
Wed, 19 Feb 2014 00:22:29 +0100 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Tue, Feb 18, 2014 at 11:49:51AM +0800, Li Guang wrote:
> Beniamino Galvani wrote:
> >According to this mail thread [1], writing to pending register seems
> >to have no effect on actual pending status of interrupts. This means
> >that the only way to clear a pending interrupt is to clear the
> >interrupt source. This patch implements such behaviour.
> >
> >[1] http://lkml.org/lkml/2013/7/6/59
> >
> >Signed-off-by: Beniamino Galvani<address@hidden>
> >---
> > hw/intc/allwinner-a10-pic.c | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> >diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
> >index bb2351f..afd57ef 100644
> >--- a/hw/intc/allwinner-a10-pic.c
> >+++ b/hw/intc/allwinner-a10-pic.c
> >@@ -49,6 +49,8 @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int
> >level)
> >
> > if (level) {
> > set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
> >+ } else {
> >+ clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
> > }
> > aw_a10_pic_update(s);
> > }
> >@@ -105,10 +107,10 @@ static void aw_a10_pic_write(void *opaque, hwaddr
> >offset, uint64_t value,
> > s->nmi = value;
> > break;
> > case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
> >- s->irq_pending[index]&= ~value;
> >+ /* Nothing to do */
> > break;
> > case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
> >- s->fiq_pending[index]&= ~value;
> >+ /* Ditto */
> > break;
> > case AW_A10_PIC_SELECT ... AW_A10_PIC_SELECT + 8:
> > s->select[index] = value;
>
> pending registers are also clear registers by a10 datasheet,
> also you found bits are marked as 'R', so, ..., contradict itself.
Yes, the datasheet is inconsistent about this because the register
can't be read-only and 'clear' at the same time.
Unfortunately at the moment I cannot test if the clearing
functionality of the pending register works on real hardware but the
idea I got from the linked discussion is that it's either not
implemented or broken and therefore interrupts remain pending until
they are disabled at the source.
Do you have a chance to try it on a real board?
Beniamino
- [Qemu-devel] [PATCH 0/7] Allwinner A10 fixes, Beniamino Galvani, 2014/02/17
- [Qemu-devel] [PATCH 5/7] allwinner-a10-pit: implement prescaler and source selection, Beniamino Galvani, 2014/02/17
- [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour, Beniamino Galvani, 2014/02/17
- Re: [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour, Li Guang, 2014/02/17
- Re: [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour,
Beniamino Galvani <=
- Re: [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour, Li Guang, 2014/02/18
- Re: [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour, Beniamino Galvani, 2014/02/22
- Re: [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour, Li Guang, 2014/02/24
- Re: [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour, Beniamino Galvani, 2014/02/24
- Re: [Qemu-devel] [PATCH 2/7] allwinner-a10-pic: fix interrupt clear behaviour, Li Guang, 2014/02/24
[Qemu-devel] [PATCH 7/7] allwinner-emac: update irq status after writes to interrupt registers, Beniamino Galvani, 2014/02/17
[Qemu-devel] [PATCH 4/7] allwinner-a10-pit: use level triggered interrupts, Beniamino Galvani, 2014/02/17
[Qemu-devel] [PATCH 3/7] allwinner-a10-pit: avoid generation of spurious interrupts, Beniamino Galvani, 2014/02/17