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[Qemu-devel] [PULL 05/15] tcg/optimize: improve known-zero bits for 32-b
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 05/15] tcg/optimize: improve known-zero bits for 32-bit ops |
Date: |
Mon, 17 Feb 2014 19:15:55 -0600 |
From: Aurelien Jarno <address@hidden>
The shl_i32 op might set some bits of the unused 32 high bits of the
mask. Fix that by clearing the unused 32 high bits for all 32-bit ops
except load/store which operate on tl values.
Reviewed-by: Paolo Bonzini <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/optimize.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 7838be2..1cf017a 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -783,6 +783,12 @@ static TCGArg *tcg_constant_folding(TCGContext *s,
uint16_t *tcg_opc_ptr,
break;
}
+ /* 32-bit ops (non 64-bit ops and non load/store ops) generate 32-bit
+ results */
+ if (!(tcg_op_defs[op].flags & (TCG_OPF_CALL_CLOBBER | TCG_OPF_64BIT)))
{
+ mask &= 0xffffffffu;
+ }
+
if (mask == 0) {
assert(def->nb_oargs == 1);
s->gen_opc_buf[op_index] = op_to_movi(op);
--
1.8.5.3
- [Qemu-devel] [PULL 00/15] tcg updates, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 02/15] tcg-arm: The shift count of op_rotl_i32 is in args[2] not args[1]., Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 01/15] TCG: Fix 32-bit host allocation typo, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 03/15] tcg/optimize: fix known-zero bits for right shift ops, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 04/15] tcg/optimize: fix known-zero bits optimization, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 05/15] tcg/optimize: improve known-zero bits for 32-bit ops,
Richard Henderson <=
- [Qemu-devel] [PULL 06/15] tcg/optimize: add known-zero bits compute for load ops, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 07/15] tcg/optimize: Handle known-zeros masks for ANDC, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 08/15] tcg/optimize: Simply some logical ops to NOT, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 09/15] tcg/optimize: Optmize ANDC X, Y, Y to MOV X, 0, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 10/15] tcg/optimize: Add more identity simplifications, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 11/15] disas/i386: Disassemble ANDN/SHLX/SHRX/SHAX, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 12/15] tcg/i386: Move TCG_CT_CONST_* to tcg-target.c, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 13/15] tcg/i386: Add tcg_out_vex_modrm, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 15/15] tcg/i386: Use SHLX/SHRX/SARX instructions, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 14/15] tcg/i386: Use ANDN instruction, Richard Henderson, 2014/02/17