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[Qemu-devel] [PATCH v3 04/31] target-arm: Implement AArch64 MIDR_EL1
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v3 04/31] target-arm: Implement AArch64 MIDR_EL1 |
Date: |
Sat, 15 Feb 2014 16:06:57 +0000 |
Implement the AArch64 view of the MIDR system register
(for AArch64 it is a simple constant, unlike the complicated
mess that TI925 imposes on the 32-bit view).
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 73dcaf6..cad6bbe 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1720,6 +1720,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
.type = ARM_CP_OVERRIDE },
+ { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0,
+ .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST },
{ .name = "CTR",
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
--
1.8.5
- [Qemu-devel] [PATCH v3 15/31] target-arm: Implement AArch64 ID and feature registers, (continued)
- [Qemu-devel] [PATCH v3 15/31] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 06/31] target-arm: Implement AArch64 TLB invalidate ops, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 25/31] target-arm: Define exception record for AArch64 exceptions, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 08/31] target-arm: Implement AArch64 memory attribute registers, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 27/31] target-arm: Add support for generating exceptions with syndrome information, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 26/31] target-arm: Provide correct syndrome information for cpreg access traps, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 14/31] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 02/31] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 18/31] target-arm: Get MMU index information correct for A64 code, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 03/31] target-arm: Implement AArch64 CurrentEL sysreg, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 04/31] target-arm: Implement AArch64 MIDR_EL1,
Peter Maydell <=
- Re: [Qemu-devel] [PATCH v3 00/31] A64 system emulation prequisites, Peter Maydell, 2014/02/25