Re: [Qemu-devel] [PATCH v2 19/35] target-arm: A64: Make cache ID registers visible to AArch64

[Peter Crosthwaite]

On Sun, Feb 9, 2014 at 9:52 PM, Peter Maydell <address@hidden> wrote:
> On 9 February 2014 02:15, Peter Crosthwaite
> <address@hidden> wrote:
>> On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell <address@hidden> wrote:
>>> -    { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
>>> +    { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
>>> +      .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
>>
>> Why is the .cp field lost in the conversion to STATE_BOTH?
>
> Because 64 bit sysregs don't have a concept of coprocessor. STATE_BOTH
> means "this is a 64 bit sysreg with a cp15 encoding in the obvious place".
> Anything other than cp15 needs split definitions anyway, so if we required
> the .cp to be specified it would always be '.cp = 15'. Essentially this is
> attempting to keep the length of cpreg definitions down by abbreviating
> parts where there isn't actually any choice.
>

Thanks,

Reviewed-by: Peter Crosthwaite <address@hidden>

> thanks
> -- PMM
>