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[Qemu-devel] [PULL 02/29] target-arm: A64: Implement remaining non-pairw
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/29] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns |
Date: |
Sat, 8 Feb 2014 15:57:37 +0000 |
Implement the SIMD 3-reg-same instructions where the size == 3 case
is reserved: SHADD, UHADD, SRHADD, URHADD, SHSUB, UHSUB, SMAX,
UMAX, SMIN, UMIN, SABD, UABD, SABA, UABA, MLA, MLS, MUL, PMUL,
SQRDMULH, SQDMULH. (None of these have scalar-3-same versions.)
This completes the non-pairwise integer instructions in this category.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 131 +++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 127 insertions(+), 4 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index e67cdbb..8d996e9 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -6556,6 +6556,27 @@ static void disas_simd_3same_logic(DisasContext *s,
uint32_t insn)
tcg_temp_free_i64(tcg_res[1]);
}
+/* Helper functions for 32 bit comparisons */
+static void gen_max_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
+{
+ tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2, op1, op2);
+}
+
+static void gen_max_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
+{
+ tcg_gen_movcond_i32(TCG_COND_GEU, res, op1, op2, op1, op2);
+}
+
+static void gen_min_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
+{
+ tcg_gen_movcond_i32(TCG_COND_LE, res, op1, op2, op1, op2);
+}
+
+static void gen_min_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
+{
+ tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2);
+}
+
/* Pairwise op subgroup of C3.6.16. */
static void disas_simd_3same_pair(DisasContext *s, uint32_t insn)
{
@@ -6656,15 +6677,13 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
unallocated_encoding(s);
return;
}
- unsupported_encoding(s, insn);
- return;
+ break;
case 0x16: /* SQDMULH, SQRDMULH */
if (size == 0 || size == 3) {
unallocated_encoding(s);
return;
}
- unsupported_encoding(s, insn);
- return;
+ break;
default:
if (size == 3 && !is_q) {
unallocated_encoding(s);
@@ -6702,6 +6721,16 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
switch (opcode) {
+ case 0x0: /* SHADD, UHADD */
+ {
+ static NeonGenTwoOpFn * const fns[3][2] = {
+ { gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 },
+ { gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 },
+ { gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 },
+ };
+ genfn = fns[size][u];
+ break;
+ }
case 0x1: /* SQADD, UQADD */
{
static NeonGenTwoOpEnvFn * const fns[3][2] = {
@@ -6712,6 +6741,26 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
genenvfn = fns[size][u];
break;
}
+ case 0x2: /* SRHADD, URHADD */
+ {
+ static NeonGenTwoOpFn * const fns[3][2] = {
+ { gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 },
+ { gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 },
+ { gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 },
+ };
+ genfn = fns[size][u];
+ break;
+ }
+ case 0x4: /* SHSUB, UHSUB */
+ {
+ static NeonGenTwoOpFn * const fns[3][2] = {
+ { gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 },
+ { gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 },
+ { gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 },
+ };
+ genfn = fns[size][u];
+ break;
+ }
case 0x5: /* SQSUB, UQSUB */
{
static NeonGenTwoOpEnvFn * const fns[3][2] = {
@@ -6782,6 +6831,38 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
genenvfn = fns[size][u];
break;
}
+ case 0xc: /* SMAX, UMAX */
+ {
+ static NeonGenTwoOpFn * const fns[3][2] = {
+ { gen_helper_neon_max_s8, gen_helper_neon_max_u8 },
+ { gen_helper_neon_max_s16, gen_helper_neon_max_u16 },
+ { gen_max_s32, gen_max_u32 },
+ };
+ genfn = fns[size][u];
+ break;
+ }
+
+ case 0xd: /* SMIN, UMIN */
+ {
+ static NeonGenTwoOpFn * const fns[3][2] = {
+ { gen_helper_neon_min_s8, gen_helper_neon_min_u8 },
+ { gen_helper_neon_min_s16, gen_helper_neon_min_u16 },
+ { gen_min_s32, gen_min_u32 },
+ };
+ genfn = fns[size][u];
+ break;
+ }
+ case 0xe: /* SABD, UABD */
+ case 0xf: /* SABA, UABA */
+ {
+ static NeonGenTwoOpFn * const fns[3][2] = {
+ { gen_helper_neon_abd_s8, gen_helper_neon_abd_u8 },
+ { gen_helper_neon_abd_s16, gen_helper_neon_abd_u16 },
+ { gen_helper_neon_abd_s32, gen_helper_neon_abd_u32 },
+ };
+ genfn = fns[size][u];
+ break;
+ }
case 0x10: /* ADD, SUB */
{
static NeonGenTwoOpFn * const fns[3][2] = {
@@ -6802,6 +6883,34 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
genfn = fns[size][u];
break;
}
+ case 0x13: /* MUL, PMUL */
+ if (u) {
+ /* PMUL */
+ assert(size == 0);
+ genfn = gen_helper_neon_mul_p8;
+ break;
+ }
+ /* fall through : MUL */
+ case 0x12: /* MLA, MLS */
+ {
+ static NeonGenTwoOpFn * const fns[3] = {
+ gen_helper_neon_mul_u8,
+ gen_helper_neon_mul_u16,
+ tcg_gen_mul_i32,
+ };
+ genfn = fns[size];
+ break;
+ }
+ case 0x16: /* SQDMULH, SQRDMULH */
+ {
+ static NeonGenTwoOpEnvFn * const fns[2][2] = {
+ { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16
},
+ { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32
},
+ };
+ assert(size == 1 || size == 2);
+ genenvfn = fns[size - 1][u];
+ break;
+ }
default:
g_assert_not_reached();
}
@@ -6812,6 +6921,20 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
genfn(tcg_res, tcg_op1, tcg_op2);
}
+ if (opcode == 0xf || opcode == 0x12) {
+ /* SABA, UABA, MLA, MLS: accumulating ops */
+ static NeonGenTwoOpFn * const fns[3][2] = {
+ { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 },
+ { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
+ { tcg_gen_add_i32, tcg_gen_sub_i32 },
+ };
+ bool is_sub = (opcode == 0x12 && u); /* MLS */
+
+ genfn = fns[size][is_sub];
+ read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
+ genfn(tcg_res, tcg_res, tcg_op1);
+ }
+
write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
tcg_temp_free_i32(tcg_res);
--
1.8.5
- [Qemu-devel] [PULL 19/29] arm_gic: Add GICC_APRn state to the GICState, (continued)
- [Qemu-devel] [PULL 19/29] arm_gic: Add GICC_APRn state to the GICState, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 28/29] hw/arm/allwinner-a10: initialize EMAC, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 05/29] target-arm: A64: Implement scalar pairwise ops, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 17/29] arm_gic: Support setting/getting binary point reg, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 26/29] util/fifo8: clear fifo head upon reset, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 23/29] disas/libvixl: Fix upstream libvixl compilation issues, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 09/29] target-arm: A64: Implement 2-register misc compares, ABS, NEG, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 21/29] rules.mak: Link with C++ if we have a C++ compiler, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 13/29] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 08/29] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 02/29] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns,
Peter Maydell <=
- [Qemu-devel] [PULL 15/29] arm_gic: Fix GIC pending behavior, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 27/29] hw/net: add support for Allwinner EMAC Fast Ethernet controller, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 20/29] rules.mak: Support .cc as a C++ source file suffix, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 03/29] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 14/29] target-arm: Add support for AArch32 64bit VCVTB and VCVTT, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 18/29] vmstate: Add uint32 2D-array support, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 24/29] disas: Implement disassembly output for A64, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 04/29] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 22/29] disas: Add subset of libvixl sources for A64 disassembler, Peter Maydell, 2014/02/08
- Re: [Qemu-devel] [PULL 00/29] target-arm queue, Peter Maydell, 2014/02/11