Re: [Qemu-devel] [PATCH v2 01/35] target-arm: Fix raw read and write functions on AArch64 registers

[Peter Maydell]

On 31 January 2014 15:56, Rob Herring <address@hidden> wrote:
> On 31 January 2014 09:45, Peter Maydell <address@hidden> wrote:
>> The raw read and write functions were using the ARM_CP_64BIT flag in
>> ri->type to determine whether to treat the register's state field as
>> uint32_t or uint64_t; however AArch64 register info structs don't use
>> that flag. Abstract out the "how big is the field?" test into a
>> function and fix it to work for AArch64 registers.

>> +/* Return true if this reginfo struct's field in the cpu state struct
>> + * is 64 bits wide.
>> + */
>> +static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
>> +{
>> +    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
>
> Won't this fail when state is ARM_CP_STATE_BOTH? That was what I found
> in testing as TTBR writes were not causing a tlb_flush.

Hmm. You're right that this won't work as it stands.
We could either fix this condition or we could make the code
that puts reginfo structs into the hashtable fix the state
so that the reginfo for the AArch64 register said _AA64
and the one for AArch32 said _AA32.

(And/or we could make that code force ARM_CP_64BIT for the AArch64
entry, but I felt it would be a bit confusing having that be
present on none of the structs in the source code but on all
of them at runtime.)

Anybody got a preference? If not I think I'll take the
path of least resistance and change this condition to

  /* Only AArch32-only non-64-bit registers have a 32 bit
   * backing field.
   */
  return (ri->state != ARM_CP_STATE_AA32) || (ri->type & ARM_CP_64BIT);

thanks
-- PMM