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[Qemu-devel] [PATCH v2 18/35] target-arm: Fix incorrect type for value a
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 18/35] target-arm: Fix incorrect type for value argument to write_raw_cp_reg |
Date: |
Fri, 31 Jan 2014 15:45:26 +0000 |
The write_raw_cp_reg's value argument should be a uint64_t, since
that's what all its callers hand it and what all the functions it
calls take. A (harmless) typo meant we were accidentally declaring
it as int64_t.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 577b060..06331dd 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -141,7 +141,7 @@ static uint64_t read_raw_cp_reg(CPUARMState *env, const
ARMCPRegInfo *ri)
}
static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
- int64_t v)
+ uint64_t v)
{
/* Raw write of a coprocessor register (as needed for migration, etc).
* Note that constant registers are treated as write-ignored; the
--
1.8.5
- [Qemu-devel] [PATCH v2 14/35] target-arm: Convert miscellaneous reginfo structs to accessfn, (continued)
- [Qemu-devel] [PATCH v2 14/35] target-arm: Convert miscellaneous reginfo structs to accessfn, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 31/35] target-arm: Implement AArch64 MPIDR, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 27/35] target-arm: Implement AArch64 SCTLR_EL1, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 12/35] target-arm: Convert performance monitor reginfo to accesfn, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 33/35] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 13/35] target-arm: Convert generic timer reginfo to accessfn, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 16/35] target-arm: Remove unnecessary code now read/write fns can't fail, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 20/35] target-arm: Implement AArch64 CurrentEL sysreg, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 06/35] target-arm: Log bad system register accesses with LOG_UNIMP, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 29/35] target-arm: Implement AArch64 VBAR_EL1, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 18/35] target-arm: Fix incorrect type for value argument to write_raw_cp_reg,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 19/35] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 17/35] target-arm: Remove failure status return from read/write_raw_cp_reg, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 04/35] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 26/35] target-arm: Implement AArch64 memory attribute registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 09/35] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 02/35] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 34/35] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 15/35] target-arm: Drop success/fail return from cpreg read and write functions, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 32/35] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 35/35] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI, Peter Maydell, 2014/01/31