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[Qemu-devel] [PULL 26/38] target-arm: A64: Add SIMD three-different ABDL
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 26/38] target-arm: A64: Add SIMD three-different ABDL instructions |
Date: |
Wed, 29 Jan 2014 13:39:53 +0000 |
Implement the absolute-difference instructions in the SIMD
three-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL,
SABDL2, UABDL, UABDL2.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 35 +++++++++++++++++++++++++++++++++--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index e8479a5..e098efd 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -5602,6 +5602,21 @@ static void handle_3rd_widening(DisasContext *s, int
is_q, int is_u, int size,
}
switch (opcode) {
+ case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
+ case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
+ {
+ TCGv_i64 tcg_tmp1 = tcg_temp_new_i64();
+ TCGv_i64 tcg_tmp2 = tcg_temp_new_i64();
+
+ tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2);
+ tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1);
+ tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE,
+ tcg_passres,
+ tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2);
+ tcg_temp_free_i64(tcg_tmp1);
+ tcg_temp_free_i64(tcg_tmp2);
+ break;
+ }
case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
@@ -5640,6 +5655,22 @@ static void handle_3rd_widening(DisasContext *s, int
is_q, int is_u, int size,
}
switch (opcode) {
+ case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
+ case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
+ if (size == 0) {
+ if (is_u) {
+ gen_helper_neon_abdl_u16(tcg_passres, tcg_op1,
tcg_op2);
+ } else {
+ gen_helper_neon_abdl_s16(tcg_passres, tcg_op1,
tcg_op2);
+ }
+ } else {
+ if (is_u) {
+ gen_helper_neon_abdl_u32(tcg_passres, tcg_op1,
tcg_op2);
+ } else {
+ gen_helper_neon_abdl_s32(tcg_passres, tcg_op1,
tcg_op2);
+ }
+ }
+ break;
case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
@@ -5739,10 +5770,10 @@ static void disas_simd_three_reg_diff(DisasContext *s,
uint32_t insn)
/* fall through */
case 0:
case 2:
- case 5:
- case 7:
unsupported_encoding(s, insn);
break;
+ case 5:
+ case 7:
case 8:
case 10:
case 12:
--
1.8.5
- [Qemu-devel] [PULL 31/38] target-arm: A64: Add simple SIMD 3-same floating point ops, (continued)
- [Qemu-devel] [PULL 31/38] target-arm: A64: Add simple SIMD 3-same floating point ops, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 29/38] target-arm: A64: Add logic ops from SIMD 3 same group, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 30/38] target-arm: A64: Add integer ops from SIMD 3-same group, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 28/38] target-arm: A64: Add top level decode for SIMD 3-same group, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 18/38] target-arm: Add support for AArch32 FP VRINTZ, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 01/38] target-arm: A64: Add SIMD ld/st multiple, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 14/38] display: avoid multi-statement macro, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 13/38] ZYNQ: Implement board MIDR control for Zynq, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 19/38] target-arm: Add support for AArch32 FP VRINTX, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 21/38] target-arm: Add set_neon_rmode helper, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 26/38] target-arm: A64: Add SIMD three-different ABDL instructions,
Peter Maydell <=
- [Qemu-devel] [PULL 07/38] target-arm: A64: Add SIMD across-lanes instructions, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 15/38] target-arm: Move arm_rmode_to_sf to a shared location., Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 05/38] target-arm: A64: Add SIMD TBL/TBLX, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 12/38] ARM: Convert MIDR to a property, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 02/38] target-arm: A64: Add SIMD ld/st single, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 25/38] target-arm: A64: Add SIMD three-different multiply accumulate insns, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 20/38] target-arm: Add support for AArch32 SIMD VRINTX, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 08/38] target-arm: A64: Add SIMD copy operations, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 03/38] target-arm: A64: Add decode skeleton for SIMD data processing insns, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 04/38] target-arm: A64: Add SIMD EXT, Peter Maydell, 2014/01/29