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Re: [Qemu-devel] [PATCH 06/24] target-arm: A64: Implement store-exclusiv
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 06/24] target-arm: A64: Implement store-exclusive for system mode |
Date: |
Wed, 22 Jan 2014 10:42:24 +0000 |
On 22 January 2014 02:19, Hu Tao <address@hidden> wrote:
> On Tue, Jan 21, 2014 at 08:12:12PM +0000, Peter Maydell wrote:
>> + if (is_pair) {
>> + TCGv_i64 addrhi = tcg_temp_new_i64();
>> + TCGv_i64 tmphi = tcg_temp_new_i64();
>> +
>> + tcg_gen_addi_i64(addrhi, addr, 1 << size);
>> + tcg_gen_qemu_ld_i64(tmphi, addrhi, get_mem_index(s), MO_TE + size);
>> + tcg_gen_brcond_i64(TCG_COND_NE, tmp, cpu_exclusive_high,
>> fail_label);
>
> s/tmp/tmphi/
Thanks, nice catch.
>> +
>> + tcg_temp_free_i64(tmphi);
>> + tcg_temp_free_i64(addrhi);
>
> Can addrhi be saved and free after doing store?
It would have to be made a local-temp to avoid the branch
trashing it. I preferred to make it a local and recalculate for
the store on the basis that the TCG backend really ought to
be capable of turning "add tmp, addr, 4; load from tmp" into
a single "load from addr+4" instruction, and having the
constant go into a local-temp would probably defeat that.
thanks
-- PMM
- [Qemu-devel] [PATCH 00/24] target-arm: implement some AArch64 system registers, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 18/24] target-arm: Implement AArch64 VBAR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 11/24] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 16/24] target-arm: Implement AArch64 SCTLR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 10/24] target-arm: Implement AArch64 MIDR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 06/24] target-arm: A64: Implement store-exclusive for system mode, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 03/24] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 12/24] target-arm: Implement AArch64 cache invalidate/clean ops, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 09/24] target-arm: Implement AArch64 CurrentEL sysreg, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 23/24] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 22/24] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 02/24] target-arm: Define names for SCTLR bits, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 08/24] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/01/21