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[Qemu-devel] [PATCH 5/9] pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 I
From: |
Igor Mammedov |
Subject: |
[Qemu-devel] [PATCH 5/9] pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from PCI bus resources |
Date: |
Thu, 9 Jan 2014 17:36:35 +0100 |
.. so that they might not be used by PCI devices.
Note:
Resort to concatenating templates with preprocessor help,
because 1.0b spec isn't supporting ConcatenateResTemplate,
as result Windows XP fails to execute PCI0._CRS method if
ConcatenateResTemplate() is used.
Signed-off-by: Igor Mammedov <address@hidden>
---
Follow up patch will expose them as motherboard resources
v2:
* add comments about holes origins for PCI/CPU hotplug and GPE0
---
hw/i386/acpi-dsdt-pci-crs.dsl | 8 +-------
hw/i386/acpi-dsdt.dsl | 32 ++++++++++++++++++++++++++++++++
hw/i386/q35-acpi-dsdt.dsl | 8 ++++++++
3 files changed, 41 insertions(+), 7 deletions(-)
diff --git a/hw/i386/acpi-dsdt-pci-crs.dsl b/hw/i386/acpi-dsdt-pci-crs.dsl
index b375a19..8b631d1 100644
--- a/hw/i386/acpi-dsdt-pci-crs.dsl
+++ b/hw/i386/acpi-dsdt-pci-crs.dsl
@@ -37,13 +37,7 @@ Scope(\_SB.PCI0) {
0x0000, // Address Translation Offset
0x0CF8, // Address Length
,, , TypeStatic)
- WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0D00, // Address Range Minimum
- 0xFFFF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0xF300, // Address Length
- ,, , TypeStatic)
+ BOARD_SPECIFIC_PCI_RESOURSES
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, // Address Space Granularity
0x000A0000, // Address Range Minimum
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index 3dc4789..f501c8d 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -35,6 +35,38 @@ DefinitionBlock (
/****************************************************************
* PCI Bus definition
****************************************************************/
+#define BOARD_SPECIFIC_PCI_RESOURSES \
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
+ 0x0000, \
+ 0x0D00, \
+ 0xADFF, \
+ 0x0000, \
+ 0xA100, \
+ ,, , TypeStatic) \
+ /* 0xae00-0xae0e hole for PCI hotplug, hw/acpi/piix4.c:PCI_HOTPLUG_ADDR
*/ \
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
+ 0x0000, \
+ 0xAE0F, \
+ 0xAEFF, \
+ 0x0000, \
+ 0x00F1, \
+ ,, , TypeStatic) \
+ /* 0xaf00-0xaf1f hole for CPU hotplug, hw/acpi/piix4.c:PIIX4_PROC_BASE */
\
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
+ 0x0000, \
+ 0xAF20, \
+ 0xAFDF, \
+ 0x0000, \
+ 0x00C0, \
+ ,, , TypeStatic) \
+ /* 0xafe0-0xafe3 hole for ACPI.GPE0, hw/acpi/piix4.c:GPE_BASE */ \
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
+ 0x0000, \
+ 0xAFE4, \
+ 0xFFFF, \
+ 0x0000, \
+ 0x501C, \
+ ,, , TypeStatic)
Scope(\_SB) {
Device(PCI0) {
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index 9a43947..f3e5921 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -48,6 +48,14 @@ DefinitionBlock (
/****************************************************************
* PCI Bus definition
****************************************************************/
+#define BOARD_SPECIFIC_PCI_RESOURSES \
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
+ 0x0000, \
+ 0x0D00, \
+ 0xFFFF, \
+ 0x0000, \
+ 0xF300, \
+ ,, , TypeStatic)
Scope(\_SB) {
Device(PCI0) {
--
1.7.1
- [Qemu-devel] [PATCH 0/9 v3] pc: CPU hotplug support for Q35, Igor Mammedov, 2014/01/09
- [Qemu-devel] [PATCH 1/9] acpi: factor out common cpu hotplug code for PIIX4/Q35, Igor Mammedov, 2014/01/09
- [Qemu-devel] [PATCH 2/9] acpi: ich9: add CPU hotplug handling to Q35 machine, Igor Mammedov, 2014/01/09
- [Qemu-devel] [PATCH 3/9] pc: make: fix dependencies: rebuild when included file is changed, Igor Mammedov, 2014/01/09
- [Qemu-devel] [PATCH 5/9] pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from PCI bus resources,
Igor Mammedov <=
- [Qemu-devel] [PATCH 4/9] pc: set PRST base in DSDT depending on chipset, Igor Mammedov, 2014/01/09
- [Qemu-devel] [PATCH 6/9] pc: Q35 DSDT: exclude CPU hotplug IO range from PCI bus resources, Igor Mammedov, 2014/01/09
- [Qemu-devel] [PATCH 8/9] pc: ACPI: unify source of CPU hotplug IO base/len, Igor Mammedov, 2014/01/09
- [Qemu-devel] [PATCH 7/9] pc: ACPI: expose PRST IO range via _CRS, Igor Mammedov, 2014/01/09
- [Qemu-devel] [PATCH 9/9] pc: ACPI: update acpi-dsdt.hex.generated q35-acpi-dsdt.hex.generated, Igor Mammedov, 2014/01/09
- Re: [Qemu-devel] [PATCH 0/9 v3] pc: CPU hotplug support for Q35, Michael S. Tsirkin, 2014/01/16