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[Qemu-devel] [PULL 47/76] target-arm: use c13_context field for CONTEXTI
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 47/76] target-arm: use c13_context field for CONTEXTIDR |
Date: |
Tue, 7 Jan 2014 20:03:43 +0000 |
From: Sergey Fedorov <address@hidden>
Use c13_context field instead of c13_fcse for CONTEXTIDR register
definition.
Signed-off-by: Sergey Fedorov <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9afec28..be52c1f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -397,7 +397,7 @@ static const ARMCPRegInfo cp_reginfo[] = {
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
.resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
{ .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 =
1,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_context),
.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write,
},
/* ??? This covers not just the impdef TLB lockdown registers but also
* some v7VMSA registers relating to TEX remap, so it is overly broad.
--
1.8.5
- [Qemu-devel] [PULL 59/76] softfloat: Fix factor 2 error for scalbn on denormal inputs, (continued)
- [Qemu-devel] [PULL 59/76] softfloat: Fix factor 2 error for scalbn on denormal inputs, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 72/76] target-arm: A64: Add extra VFP fixed point conversion helpers, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 60/76] softfloat: Add float32_to_uint64(), Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 76/76] target-arm: A64: Add support for FCVT between half, single and double, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 51/76] arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 69/76] target-arm: Prepare VFP_CONV_FIX helpers for A64 uses, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 54/76] softfloat: Add float to 16bit integer conversions., Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 49/76] arm/xilinx_zynq: Always instantiate the GEMs, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 62/76] softfloat: Fix float64_to_uint32, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 63/76] softfloat: Fix float64_to_uint32_round_to_zero, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 47/76] target-arm: use c13_context field for CONTEXTIDR,
Peter Maydell <=
- [Qemu-devel] [PULL 64/76] softfloat: Provide complete set of accessors for fp state, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 20/76] target-arm: Widen exclusive-access support struct fields to 64 bits, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 48/76] target-arm: remove raw_read|write duplication, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 19/76] target-arm: aarch64: add support for ld lit, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 23/76] linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 35/76] target-arm: Give the FPSCR rounding modes names, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 34/76] target-arm: A64: Add support for floating point cond select, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 36/76] char/cadence_uart: Mark struct fields as public/private, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 56/76] softfloat: Make the int-to-float functions take exact-width types, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 13/76] target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder, Peter Maydell, 2014/01/07