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[Qemu-devel] [PULL 70/76] target-arm: Rename A32 VFP conversion helpers
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 70/76] target-arm: Rename A32 VFP conversion helpers |
Date: |
Tue, 7 Jan 2014 20:04:06 +0000 |
From: Will Newton <address@hidden>
The VFP conversion helpers for A32 round to zero as this is the only
rounding mode supported. Rename these helpers to make it clear that
they round to zero and are not suitable for use in the AArch64 code.
Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/helper.c | 19 ++++++++++++++-----
target-arm/helper.h | 16 ++++++++--------
target-arm/translate.c | 24 +++++++++++++-----------
3 files changed, 35 insertions(+), 24 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5579565..db4f516 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3976,7 +3976,7 @@ float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
}
/* VFP3 fixed point conversion. */
-#define VFP_CONV_FIX(name, p, fsz, isz, itype) \
+#define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
void *fpstp) \
{ \
@@ -3984,9 +3984,12 @@ float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x,
uint32_t shift, \
float##fsz tmp; \
tmp = itype##_to_##float##fsz(x, fpst); \
return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
-} \
-uint##isz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
- void *fpstp) \
+}
+
+#define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
+uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
+ uint32_t shift, \
+ void *fpstp) \
{ \
float_status *fpst = fpstp; \
float##fsz tmp; \
@@ -3995,9 +3998,13 @@ uint##isz##_t HELPER(vfp_to##name##p)(float##fsz x,
uint32_t shift, \
return 0; \
} \
tmp = float##fsz##_scalbn(x, shift, fpst); \
- return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
+ return float##fsz##_to_##itype##round(tmp, fpst); \
}
+#define VFP_CONV_FIX(name, p, fsz, isz, itype) \
+VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
+VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero)
+
VFP_CONV_FIX(sh, d, 64, 64, int16)
VFP_CONV_FIX(sl, d, 64, 64, int32)
VFP_CONV_FIX(uh, d, 64, 64, uint16)
@@ -4007,6 +4014,8 @@ VFP_CONV_FIX(sl, s, 32, 32, int32)
VFP_CONV_FIX(uh, s, 32, 32, uint16)
VFP_CONV_FIX(ul, s, 32, 32, uint32)
#undef VFP_CONV_FIX
+#undef VFP_CONV_FIX_FLOAT
+#undef VFP_CONV_FLOAT_FIX_ROUND
/* Half precision conversions. */
static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status
*s)
diff --git a/target-arm/helper.h b/target-arm/helper.h
index dd1160e..b785623 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -115,14 +115,14 @@ DEF_HELPER_2(vfp_tosid, i32, f64, ptr)
DEF_HELPER_2(vfp_tosizs, i32, f32, ptr)
DEF_HELPER_2(vfp_tosizd, i32, f64, ptr)
-DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
-DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
-DEF_HELPER_3(vfp_touhs, i32, f32, i32, ptr)
-DEF_HELPER_3(vfp_touls, i32, f32, i32, ptr)
-DEF_HELPER_3(vfp_toshd, i64, f64, i32, ptr)
-DEF_HELPER_3(vfp_tosld, i64, f64, i32, ptr)
-DEF_HELPER_3(vfp_touhd, i64, f64, i32, ptr)
-DEF_HELPER_3(vfp_tould, i64, f64, i32, ptr)
+DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, ptr)
+DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, ptr)
+DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, ptr)
+DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, ptr)
+DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr)
+DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr)
+DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
+DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
DEF_HELPER_3(vfp_shtos, f32, i32, i32, ptr)
DEF_HELPER_3(vfp_sltos, f32, i32, i32, ptr)
DEF_HELPER_3(vfp_uhtos, f32, i32, i32, ptr)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index d04fc9f..8d240e1 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -1098,27 +1098,29 @@ VFP_GEN_FTOI(tosi)
VFP_GEN_FTOI(tosiz)
#undef VFP_GEN_FTOI
-#define VFP_GEN_FIX(name) \
+#define VFP_GEN_FIX(name, round) \
static inline void gen_vfp_##name(int dp, int shift, int neon) \
{ \
TCGv_i32 tmp_shift = tcg_const_i32(shift); \
TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
if (dp) { \
- gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, statusptr); \
+ gen_helper_vfp_##name##d##round(cpu_F0d, cpu_F0d, tmp_shift, \
+ statusptr); \
} else { \
- gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, statusptr); \
+ gen_helper_vfp_##name##s##round(cpu_F0s, cpu_F0s, tmp_shift, \
+ statusptr); \
} \
tcg_temp_free_i32(tmp_shift); \
tcg_temp_free_ptr(statusptr); \
}
-VFP_GEN_FIX(tosh)
-VFP_GEN_FIX(tosl)
-VFP_GEN_FIX(touh)
-VFP_GEN_FIX(toul)
-VFP_GEN_FIX(shto)
-VFP_GEN_FIX(slto)
-VFP_GEN_FIX(uhto)
-VFP_GEN_FIX(ulto)
+VFP_GEN_FIX(tosh, _round_to_zero)
+VFP_GEN_FIX(tosl, _round_to_zero)
+VFP_GEN_FIX(touh, _round_to_zero)
+VFP_GEN_FIX(toul, _round_to_zero)
+VFP_GEN_FIX(shto, )
+VFP_GEN_FIX(slto, )
+VFP_GEN_FIX(uhto, )
+VFP_GEN_FIX(ulto, )
#undef VFP_GEN_FIX
static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv_i32 addr)
--
1.8.5
- [Qemu-devel] [PULL 65/76] softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal, (continued)
- [Qemu-devel] [PULL 65/76] softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 53/76] softfloat: Fix exception flag handling for float32_to_float16(), Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 03/76] target-arm: A64: add support for ld/st with reg offset, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 75/76] target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 18/76] target-arm: A64: add support for conditional compare insns, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 12/76] target-arm: Update generic cpreg code for AArch64, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 11/76] target-arm: Pull "add one cpreg to hashtable" into its own function, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 10/76] target-arm: A64: implement FMOV, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 67/76] softfloat: Refactor code handling various rounding modes, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 71/76] target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 70/76] target-arm: Rename A32 VFP conversion helpers,
Peter Maydell <=
- [Qemu-devel] [PULL 66/76] softfloat: Add float16 <=> float64 conversion functions, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 68/76] softfloat: Add support for ties-away rounding, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 61/76] softfloat: Fix float64_to_uint64_round_to_zero, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 73/76] target-arm: A64: Add floating-point<->fixed-point instructions, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 59/76] softfloat: Fix factor 2 error for scalbn on denormal inputs, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 72/76] target-arm: A64: Add extra VFP fixed point conversion helpers, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 60/76] softfloat: Add float32_to_uint64(), Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 76/76] target-arm: A64: Add support for FCVT between half, single and double, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 51/76] arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 69/76] target-arm: Prepare VFP_CONV_FIX helpers for A64 uses, Peter Maydell, 2014/01/07