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[Qemu-devel] [PULL 26/52] target-arm: A64: Add support for dumping AArch
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 26/52] target-arm: A64: Add support for dumping AArch64 VFP register state |
Date: |
Mon, 6 Jan 2014 11:30:31 +0000 |
From: Alexander Graf <address@hidden>
When dumping the current CPU state, we can also get a request
to dump the FPU state along with the CPU's integer state.
Add support to dump the VFP state when that flag is set, so that
we can properly debug code that modifies floating point registers.
Signed-off-by: Alexander Graf <address@hidden>
[WN: Commit message tweak, rebased. Output all registers, two per-line.]
Signed-off-by: Will Newton <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 40c6fc4..326f36d 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -119,6 +119,22 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
psr & PSTATE_C ? 'C' : '-',
psr & PSTATE_V ? 'V' : '-');
cpu_fprintf(f, "\n");
+
+ if (flags & CPU_DUMP_FPU) {
+ int numvfpregs = 32;
+ for (i = 0; i < numvfpregs; i += 2) {
+ uint64_t vlo = float64_val(env->vfp.regs[i * 2]);
+ uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]);
+ cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ",
+ i, vhi, vlo);
+ vlo = float64_val(env->vfp.regs[(i + 1) * 2]);
+ vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]);
+ cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n",
+ i + 1, vhi, vlo);
+ }
+ cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
+ vfp_get_fpcr(env), vfp_get_fpsr(env));
+ }
}
static int get_mem_index(DisasContext *s)
--
1.8.5
- [Qemu-devel] [PULL 37/52] char/cadence_uart: Add missing uart_update_state, (continued)
- [Qemu-devel] [PULL 37/52] char/cadence_uart: Add missing uart_update_state, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 47/52] target-arm: use c13_context field for CONTEXTIDR, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 36/52] char/cadence_uart: Mark struct fields as public/private, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 35/52] target-arm: Give the FPSCR rounding modes names, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 34/52] target-arm: A64: Add support for floating point cond select, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 33/52] target-arm: A64: Add support for floating point conditional compare, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 45/52] char/cadence_uart: Delete redundant rx rst logic, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 31/52] target-arm: A64: Add fmov (scalar, immediate) instruction, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 42/52] char/cadence_uart: Remove TX timer & add TX FIFO state, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 30/52] target-arm: A64: Add "Floating-point data-processing (3 source)" insns, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 26/52] target-arm: A64: Add support for dumping AArch64 VFP register state,
Peter Maydell <=
- [Qemu-devel] [PULL 28/52] target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 27/52] target-arm: A64: Fix vector register access on bigendian hosts, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 32/52] target-arm: A64: Add support for floating point compare, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 24/52] .travis.yml: Add aarch64-* targets, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 25/52] default-configs: Add config for aarch64-linux-user, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 21/52] target-arm: A64: support for ld/st/cl exclusive, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 08/52] target-arm: A64: implement SVC, BRK, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 19/52] target-arm: aarch64: add support for ld lit, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 07/52] target-arm: A64: add support for 3 src data proc insns, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 29/52] target-arm: A64: Add "Floating-point data-processing (2 source)" insns, Peter Maydell, 2014/01/06