Re: [Qemu-devel] [PATCH v2 15/25] target-arm: A64: Implement minimal set of EL0-visible sysregs

[Peter Crosthwaite]

On Sat, Jan 4, 2014 at 9:35 PM, Peter Maydell <address@hidden> wrote:
> On 4 January 2014 02:34, Peter Crosthwaite <address@hidden> wrote:
>> On Mon, Dec 23, 2013 at 8:49 AM, Peter Maydell <address@hidden> wrote:
>>> +static const ARMCPRegInfo v8_cp_reginfo[] = {
>>> +    /* Minimal set of EL0-visible registers. This will need to be expanded
>>> +     * significantly for system emulation of AArch64 CPUs.
>>> +     */
>>> +    { .name = "NZCV", .state = ARM_CP_STATE_AA64,
>>> +      .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
>>> +      .access = PL0_RW, .type = ARM_CP_NZCV },
>>> +    {. name = "FPCR", .state = ARM_CP_STATE_AA64,
>>> +     .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
>>> +     .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = 
>>> aa64_fpcr_write },
>>
>> Indentation and spacing looks inconsistent.
>
> So it does (I didn't even know it was syntactically valid to leave
> a space after the '.' like that...) . Will fix.
>

FWIW, I think in ".foo" the "." and "foo" will still be lexed as two
tokens by compilers so the standard rule of "whitespace doesn't
matter" applies and the parser has to sort it out.

Checkpatch could probably use a rule though.

> Do you mind if I don't do a respin just for this?
>

Not just for this, although I had a second read through and have a
comment on the CTR (separate mail). But i'd rather see it go through
considering the issue is flagged fixme, so just pending the
whitespace:

Reviewed-by: Peter Crosthwaite <address@hidden>

(I haven't gone line by line on the TCG stuff, but Richard has RB'd it
so I'm assuming thats covered).

Regards,
Peter

> thanks
> -- PMM
>