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[Qemu-devel] [PATCH target-arm v4 3/3] zynq_slcr: Implement CPU reset
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v4 3/3] zynq_slcr: Implement CPU reset |
Date: |
Wed, 1 Jan 2014 23:32:09 -0800 |
Implement the CPU reset function of the A9_CPU_RST_CTRL register
(offset 0x244).
Signed-off-by: Peter Crosthwaite <address@hidden>
---
changed from v3:
Author reset
Use CPU reset rather than device reset
use extract32 rather than << &.
Removed halting functionality
changed from v2:
used device halting API instead of talking to the cpu.
hw/misc/zynq_slcr.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
index 83ffc3b..0f94e03 100644
--- a/hw/misc/zynq_slcr.c
+++ b/hw/misc/zynq_slcr.c
@@ -116,6 +116,8 @@ typedef enum {
RESET_MAX
} ResetValues;
+#define A9_CPU_RST_CTRL_RST_SHIFT 0
+
#define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
#define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)
@@ -349,6 +351,7 @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
ZynqSLCRState *s = (ZynqSLCRState *)opaque;
+ int i;
DB_PRINT("offset: %08x data: %08x\n", (unsigned)offset, (unsigned)val);
@@ -403,6 +406,15 @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
goto bad_reg;
}
s->reset[(offset - 0x200) / 4] = val;
+ if (offset - 0x200 == A9_CPU * 4) { /* CPU Reset */
+ for (i = 0; i < NUM_CPUS && s->cpus[i]; ++i) {
+ bool rst = extract32(val, A9_CPU_RST_CTRL_RST_SHIFT + i,
1);
+ if (rst) {
+ DB_PRINT("resetting cpu %d\n", i);
+ cpu_reset(s->cpus[i]);
+ }
+ }
+ }
break;
case 0x300:
s->apu_ctrl = val;
--
1.8.5.2