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Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP register
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers |
Date: |
Mon, 23 Dec 2013 09:05:12 +0000 |
On 23 December 2013 07:43, Fedorov Sergey <address@hidden> wrote:
>
> On 12/20/2013 06:33 PM, Peter Maydell wrote:
>> This sounds like it could work, though there are some wrinkles for
>> registers with readfns/writefns -- do we have extra s vs ns read/write
>> functions, or just one set of functions which has to look in env->ns to
>> figure out whether to use the S or NS version?
>
> What about defining a separate ARMCPRegInfo for each banked AArch32
> system register? I think it would be close to AArch64 concept. It would
> allow to use separate read/write handlers if necessary or reuse the same
> handlers otherwise. When the handlers is not used, the translation code
> would simply lookup the ARMCPRegInfo for corresponding secure state and
> use the field offset.
Yes, I was thinking about that the other day -- add the S/NS to the
set of things in the hash table key, and have the 32 bit MCR/MRC
code pass in the right value to get the correct banked register out.
(We'd have to make all the non-banked registers go into the
hashtable twice, though, but that's not a big deal I think.)
thanks
-- PMM
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, (continued)
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, Fedorov Sergey, 2013/12/20
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, Peter Maydell, 2013/12/20
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, Fedorov Sergey, 2013/12/20
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, Fedorov Sergey, 2013/12/20
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, Peter Crosthwaite, 2013/12/21
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, Peter Maydell, 2013/12/22
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, Fedorov Sergey, 2013/12/23
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers, Fedorov Sergey, 2013/12/23
- Re: [Qemu-devel] [RFC PATCH 18/21] target-arm: switch banked CP registers,
Peter Maydell <=
[Qemu-devel] [RFC PATCH 15/21] target-arm: add banked coprocessor register type, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 16/21] target-arm: convert appropriate coprocessor registers to banked type, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 13/21] target-arm: add SDER definition, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 02/21] target-arm: move SCR & VBAR into TrustZone register list, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 06/21] target-arm: add arm_is_secure() helper, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 20/21] target-arm: implement SMC instruction, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 19/21] target-arm: add MVBAR support, Sergey Fedorov, 2013/12/03