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[Qemu-devel] [PATCH v2 00/25] target-arm: A64 decoder sets 3 and 4: ever
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 00/25] target-arm: A64 decoder sets 3 and 4: everything but fp & simd |
Date: |
Sun, 22 Dec 2013 22:49:42 +0000 |
Hi; this is the second version of a64-third-fourth-set, which
implements support for more or less all A64 instructions except
* FP [we support simple FP register load/store and
transfer to/from the general purpose registers]
* Neon
* system instructions (either ones only available to system
mode or which only make sense for system mode like LDRT)
(There may also be one or two obscure gaps like the CRC32 instruction.)
Changes v1->v2:
* finally got the ld/st pair decode correct
* cleaned up the other ld/st decode to use extract32 rather than bitops
* special case the simple-multiply in 3-src data ops
* move set_pc in mrs/msr down to the end-of-loop handling
* fix use of tcg temp over bblk end and possible gcc warning in cond-compare
* use new qemu ld ops in ldst excl
* revised version of sysregs support:
+ new .state field to specify whether register is AA64, AA32 or both
+ support shared register definitions between both states
+ new patch pulling the inner loop body of the 'define a reginfo'
function out into its own function, for clarity
+ move the AA64 TLS register definitions to be together with the AA32
ones rather than in a completely different part of the file
* added a couple of minor bugfixes to aarch64 linux-user support found
in testing (the clone bugfix in particular is necessary for fork())
* added a patch to add the aarch64 targets to the travis test matrix
(That looks like a long list but it's mostly minor stuff apart from
the adjustments to sysregs support.)
This patchset sits on top of upstream master (yay); git tree
available at:
git://git.linaro.org/people/peter.maydell/qemu-arm.git a64-third-fourth-set
web UI:
https://git.linaro.org/people/peter.maydell/qemu-arm.git/shortlog/refs/heads/a64-third-fourth-set
(My plan for the next patchset is basically "softfloat
fixes and all of FP"; we have working and tested code
that basically just needs a touch more cleanup.)
thanks
-- PMM
Alex Bennée (6):
target-arm: A64: add support for ld/st unsigned imm
target-arm: A64: add support for ld/st with reg offset
target-arm: A64: add support for ld/st with index
target-arm: A64: add support for add, addi, sub, subi
target-arm: A64: add support for move wide instructions
.travis.yml: Add aarch64-* targets
Alexander Graf (3):
target-arm: A64: add support for 3 src data proc insns
target-arm: A64: implement SVC, BRK
target-arm: aarch64: add support for ld lit
Claudio Fontana (3):
target-arm: A64: add support for add/sub with carry
target-arm: A64: add support for conditional compare insns
linux-user: AArch64: define TARGET_CLONE_BACKWARDS
Michael Matz (1):
target-arm: A64: support for ld/st/cl exclusive
Peter Maydell (11):
target-arm: A64: add support for ld/st pair
target-arm: A64: Add decoder skeleton for FP instructions
target-arm: A64: implement FMOV
target-arm: Pull "add one cpreg to hashtable" into its own function
target-arm: Update generic cpreg code for AArch64
target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder
target-arm: A64: Implement MRS/MSR/SYS/SYSL
target-arm: A64: Implement minimal set of EL0-visible sysregs
target-arm: Widen thread-local register state fields to 64 bits
target-arm: Widen exclusive-access support struct fields to 64 bits
default-configs: Add config for aarch64-linux-user
Will Newton (1):
linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext
.travis.yml | 1 +
default-configs/aarch64-linux-user.mak | 3 +
linux-user/aarch64/syscall.h | 1 +
linux-user/aarch64/target_cpu.h | 5 +-
linux-user/arm/target_cpu.h | 2 +-
linux-user/main.c | 154 ++-
linux-user/signal.c | 10 +-
target-arm/cpu.h | 109 +-
target-arm/helper.c | 284 ++++-
target-arm/kvm-consts.h | 37 +
target-arm/machine.c | 12 +-
target-arm/translate-a64.c | 1949 ++++++++++++++++++++++++++++++--
target-arm/translate.c | 72 +-
target-arm/translate.h | 2 +
14 files changed, 2439 insertions(+), 202 deletions(-)
create mode 100644 default-configs/aarch64-linux-user.mak
--
1.8.5
- [Qemu-devel] [PATCH v2 00/25] target-arm: A64 decoder sets 3 and 4: everything but fp & simd,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 19/25] target-arm: aarch64: add support for ld lit, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 17/25] target-arm: A64: add support for add/sub with carry, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 25/25] default-configs: Add config for aarch64-linux-user, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 23/25] linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 11/25] target-arm: Pull "add one cpreg to hashtable" into its own function, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 10/25] target-arm: A64: implement FMOV, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 04/25] target-arm: A64: add support for ld/st with index, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 18/25] target-arm: A64: add support for conditional compare insns, Peter Maydell, 2013/12/22