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[Qemu-devel] [PATCH v2 0/9] target-sh4: optimizations and cleanups
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH v2 0/9] target-sh4: optimizations and cleanups |
Date: |
Sun, 22 Dec 2013 12:50:30 +0100 |
This patchset improves the SH4 emulation by using the lately added
TCG instructions, namely add2, sub2 and movcond. For that the T, Q and
M bits are split out from the SR register.
The last three patches are doing cleanup in the code.
Changes v1 -> v2:
- rebased
- added last patch
Aurelien Jarno (9):
target-sh4: use bit number for SR constants
target-sh4: Split out T from SR
target-sh4: optimize addc using add2
target-sh4: optimize subc using sub2
target-sh4: optimize negc using add2 and sub2
target-sh4: split out Q and M from of SR and optimize div1
target-sh4: factorize fmov implementation
target-sh4: remove dead code
target-sh4: simplify tas instruction
target-sh4/cpu.c | 3 +-
target-sh4/cpu.h | 51 +++++---
target-sh4/gdbstub.c | 8 +-
target-sh4/helper.c | 29 ++---
target-sh4/helper.h | 1 -
target-sh4/op_helper.c | 148 +----------------------
target-sh4/translate.c | 313 ++++++++++++++++++++++++------------------------
7 files changed, 221 insertions(+), 332 deletions(-)
--
1.7.10.4
- [Qemu-devel] [PATCH v2 0/9] target-sh4: optimizations and cleanups,
Aurelien Jarno <=
- [Qemu-devel] [PATCH v2 6/9] target-sh4: split out Q and M from of SR and optimize div1, Aurelien Jarno, 2013/12/22
- [Qemu-devel] [PATCH v2 3/9] target-sh4: optimize addc using add2, Aurelien Jarno, 2013/12/22
- [Qemu-devel] [PATCH v2 2/9] target-sh4: Split out T from SR, Aurelien Jarno, 2013/12/22
- [Qemu-devel] [PATCH v2 5/9] target-sh4: optimize negc using add2 and sub2, Aurelien Jarno, 2013/12/22
- [Qemu-devel] [PATCH v2 9/9] target-sh4: simplify tas instruction, Aurelien Jarno, 2013/12/22