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[Qemu-devel] [PATCH 5/8] target-sh4: optimize negc using add2 and sub2
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 5/8] target-sh4: optimize negc using add2 and sub2 |
Date: |
Sat, 21 Dec 2013 17:59:02 +0100 |
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-sh4/translate.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 3af9ccd..3a3b2b6 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -796,12 +796,12 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0x600a: /* negc Rm,Rn */
{
- TCGv t0 = tcg_temp_new();
- tcg_gen_neg_i32(t0, REG(B7_4));
- tcg_gen_sub_i32(REG(B11_8), t0, cpu_sr_t);
- tcg_gen_setcondi_i32(TCG_COND_GTU, cpu_sr_t, t0, 0);
- tcg_gen_setcond_i32(TCG_COND_GTU, t0, REG(B11_8), t0);
- tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, t0);
+ TCGv t0 = tcg_const_i32(0);
+ tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
+ REG(B7_4), t0, cpu_sr_t, t0);
+ tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t,
+ t0, t0, REG(B11_8), cpu_sr_t);
+ tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1);
tcg_temp_free(t0);
}
return;
--
1.7.10.4
- [Qemu-devel] [PATCH 0/8] target-sh4: optimizations and cleanups, Aurelien Jarno, 2013/12/21
- [Qemu-devel] [PATCH 5/8] target-sh4: optimize negc using add2 and sub2,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 4/8] target-sh4: optimize subc using sub2, Aurelien Jarno, 2013/12/21
- [Qemu-devel] [PATCH 2/8] target-sh4: Split out T from SR, Aurelien Jarno, 2013/12/21
- [Qemu-devel] [PATCH 8/8] target-sh4: remove dead code, Aurelien Jarno, 2013/12/21
- [Qemu-devel] [PATCH 7/8] target-sh4: factorize fmov implementation, Aurelien Jarno, 2013/12/21
- [Qemu-devel] [PATCH 6/8] target-sh4: split out Q and M from of SR and optimize div1, Aurelien Jarno, 2013/12/21
- [Qemu-devel] [PATCH 3/8] target-sh4: optimize addc using add2, Aurelien Jarno, 2013/12/21
- [Qemu-devel] [PATCH 1/8] target-sh4: use bit number for SR constants, Aurelien Jarno, 2013/12/21