qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-devel] [PATCH 3/5] target-ppc: fix SPR_CTRL/SPR_UCTRL register num


From: Alexey Kardashevskiy
Subject: [Qemu-devel] [PATCH 3/5] target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers
Date: Fri, 20 Dec 2013 17:41:32 +1100

Assuming that "U" in SPR_UCTRL is for "user", there is inconsistency with
970 user manuals/P5-bookIV/PowerISA204 which define the number as:

                       priviledged
#   spr5-9 spr0-4 name mtspr mfspr len cat
136 00100  01000  CTRL   -    no    32  S
152 00100  11000  CTRL  yes    -    32  S

This swaps the numbers. No effect from this change is expected though.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
 target-ppc/cpu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 4369e7c..51bcd4a 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1250,7 +1250,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
 #define SPR_MPC_EIE           (0x050)
 #define SPR_MPC_EID           (0x051)
 #define SPR_MPC_NRI           (0x052)
-#define SPR_CTRL              (0x088)
+#define SPR_UCTRL             (0x088)
 #define SPR_MPC_CMPA          (0x090)
 #define SPR_MPC_CMPB          (0x091)
 #define SPR_MPC_CMPC          (0x092)
@@ -1259,7 +1259,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
 #define SPR_MPC_DER           (0x095)
 #define SPR_MPC_COUNTA        (0x096)
 #define SPR_MPC_COUNTB        (0x097)
-#define SPR_UCTRL             (0x098)
+#define SPR_CTRL              (0x098)
 #define SPR_MPC_CMPE          (0x098)
 #define SPR_MPC_CMPF          (0x099)
 #define SPR_MPC_CMPG          (0x09A)
-- 
1.8.4.rc4




reply via email to

[Prev in Thread] Current Thread [Next in Thread]