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[Qemu-devel] [V3 PATCH 10/14] target-ppc: Fix and enable fri[mnpz]
From: |
Tom Musta |
Subject: |
[Qemu-devel] [V3 PATCH 10/14] target-ppc: Fix and enable fri[mnpz] |
Date: |
Wed, 18 Dec 2013 14:49:03 -0600 |
The fri* series of instructions was introduced prior to ISA 2.06 and
is supported on Power7 and Power8 hardware. However, the instruction
is still considered illegal in the P7 and P8 QEMU emulation models.
This patch enables these instructions for the P7 and P8 machines.
Also, the existing helper is modified to correctly handle some of
the boundary cases (NaNs and the inexact flag).
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/fpu_helper.c | 12 ++++++------
target-ppc/translate_init.c | 2 ++
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 18b9bcd..981f002 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -668,18 +668,18 @@ static inline uint64_t do_fri(CPUPPCState *env, uint64_t
arg,
if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN round */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
- POWERPC_EXCP_FP_VXCVI, 1);
- } else if (unlikely(float64_is_quiet_nan(farg.d) ||
- float64_is_infinity(farg.d))) {
- /* qNan / infinity round */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
+ farg.ll = float64_default_nan | 0x0008000000000000ul;
} else {
set_float_rounding_mode(rounding_mode, &env->fp_status);
farg.ll = float64_round_to_int(farg.d, &env->fp_status);
/* Restore rounding mode from FPSCR */
fpscr_set_rounding_mode(env);
+
+ /* fri* does not set FPSCR[XX] */
+ env->fp_status.float_exception_flags &= ~float_flag_inexact;
}
+ helper_float_check_status(env);
return farg.ll;
}
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 491e56c..7bb9bbc 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7228,6 +7228,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
@@ -7265,6 +7266,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
--
1.7.1
- [Qemu-devel] [V3 PATCH 04/14] target-ppc: Add ISA2.06 divde[o] Instructions, (continued)
- [Qemu-devel] [V3 PATCH 04/14] target-ppc: Add ISA2.06 divde[o] Instructions, Tom Musta, 2013/12/18
- [Qemu-devel] [V3 PATCH 05/14] target-ppc: Add ISA 2.06 divwe[u][o] Instructions, Tom Musta, 2013/12/18
- [Qemu-devel] [V3 PATCH 07/14] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions, Tom Musta, 2013/12/18
- [Qemu-devel] [V3 PATCH 08/14] target-ppc: Add ISA2.06 Float to Integer Instructions, Tom Musta, 2013/12/18
- [Qemu-devel] [V3 PATCH 09/14] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions, Tom Musta, 2013/12/18
- [Qemu-devel] [V3 PATCH 10/14] target-ppc: Fix and enable fri[mnpz],
Tom Musta <=
- [Qemu-devel] [V3 PATCH 11/14] target-ppc: Add ISA 2.06 ftdiv Instruction, Tom Musta, 2013/12/18
- [Qemu-devel] [V3 PATCH 12/14] target-ppc: Add ISA 2.06 ftsqrt, Tom Musta, 2013/12/18
- [Qemu-devel] [V3 PATCH 13/14] target-ppc: Enable frsqrtes on Power7 and Power8, Tom Musta, 2013/12/18
- [Qemu-devel] [V3 PATCH 14/14] target-ppc: Add ISA2.06 lfiwzx Instruction, Tom Musta, 2013/12/18