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[Qemu-devel] [PULL 38/62] target-arm: A64: add support for conditional s
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 38/62] target-arm: A64: add support for conditional select |
Date: |
Tue, 17 Dec 2013 20:28:56 +0000 |
From: Claudio Fontana <address@hidden>
This patch adds support for the instruction group "C3.5.6
Conditional select": CSEL, CSINC, CSINV, CSNEG.
Signed-off-by: Claudio Fontana <address@hidden>
[PMM: Improved code generated in the nomatch case as per RTH suggestions]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 67 ++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 65 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 5ae3a85..13eedf4 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -724,10 +724,73 @@ static void disas_cc_reg(DisasContext *s, uint32_t insn)
unsupported_encoding(s, insn);
}
-/* Conditional select */
+/* C3.5.6 Conditional select
+ * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
+ * +----+----+---+-----------------+------+------+-----+------+------+
+ * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
+ * +----+----+---+-----------------+------+------+-----+------+------+
+ */
static void disas_cond_select(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
+ unsigned int sf, else_inv, rm, cond, else_inc, rn, rd;
+ TCGv_i64 tcg_rd, tcg_src;
+
+ if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) {
+ /* S == 1 or op2<1> == 1 */
+ unallocated_encoding(s);
+ return;
+ }
+ sf = extract32(insn, 31, 1);
+ else_inv = extract32(insn, 30, 1);
+ rm = extract32(insn, 16, 5);
+ cond = extract32(insn, 12, 4);
+ else_inc = extract32(insn, 10, 1);
+ rn = extract32(insn, 5, 5);
+ rd = extract32(insn, 0, 5);
+
+ if (rd == 31) {
+ /* silly no-op write; until we use movcond we must special-case
+ * this to avoid a dead temporary across basic blocks.
+ */
+ return;
+ }
+
+ tcg_rd = cpu_reg(s, rd);
+
+ if (cond >= 0x0e) { /* condition "always" */
+ tcg_src = read_cpu_reg(s, rn, sf);
+ tcg_gen_mov_i64(tcg_rd, tcg_src);
+ } else {
+ /* OPTME: we could use movcond here, at the cost of duplicating
+ * a lot of the arm_gen_test_cc() logic.
+ */
+ int label_match = gen_new_label();
+ int label_continue = gen_new_label();
+
+ arm_gen_test_cc(cond, label_match);
+ /* nomatch: */
+ tcg_src = cpu_reg(s, rm);
+
+ if (else_inv && else_inc) {
+ tcg_gen_neg_i64(tcg_rd, tcg_src);
+ } else if (else_inv) {
+ tcg_gen_not_i64(tcg_rd, tcg_src);
+ } else if (else_inc) {
+ tcg_gen_addi_i64(tcg_rd, tcg_src, 1);
+ } else {
+ tcg_gen_mov_i64(tcg_rd, tcg_src);
+ }
+ if (!sf) {
+ tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
+ }
+ tcg_gen_br(label_continue);
+ /* match: */
+ gen_set_label(label_match);
+ tcg_src = read_cpu_reg(s, rn, sf);
+ tcg_gen_mov_i64(tcg_rd, tcg_src);
+ /* continue: */
+ gen_set_label(label_continue);
+ }
}
/* Data-processing (1 source) */
--
1.8.5
- [Qemu-devel] [PULL 58/62] hw/timer: add allwinner a10 timer, (continued)
- [Qemu-devel] [PULL 58/62] hw/timer: add allwinner a10 timer, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 52/62] hw/arm/digic: prepare DIGIC-based boards support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 48/62] host-utils: add clrsb32/64 - count leading redundant sign bits, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 47/62] target-arm: A64: add support for bitfield insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 46/62] target-arm: A64: add support for 1-src REV insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 54/62] hw/arm/digic: add UART support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 43/62] target-arm: A64: add support for 2-src shift reg insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 37/62] target-arm: A64: add support for compare and branch imm, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 59/62] hw/intc: add allwinner A10 interrupt controller, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 39/62] target-arm: A64: add support for logical (shifted register), Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 38/62] target-arm: A64: add support for conditional select,
Peter Maydell <=
- [Qemu-devel] [PULL 55/62] hw/arm/digic: add NOR ROM support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 44/62] target-arm: A64: add support for 1-src data processing and CLZ, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 49/62] target-arm: A64: add support for 1-src CLS insn, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 41/62] target-arm: A64: add support for EXTR, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 22/62] configure: Enable KVM for aarch64 host/target combination, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 26/62] target-arm: Split A64 from A32/T32 gen_intermediate_code_internal(), Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 02/62] rename pflash_t member width to bank_width, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 24/62] hw/arm/boot: Add boot support for AArch64 processor, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 13/62] arm/highbank: Fix CBAR initialisation, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 03/62] Add device-width property to pflash_cfi01, Peter Maydell, 2013/12/17