Re: [Qemu-devel] [PATCH V17 00/11] Add support for binding guest numa nodes to host numa nodes

[Marcelo Tosatti]

On Fri, Dec 06, 2013 at 10:06:37AM +0100, Paolo Bonzini wrote:
> Il 04/12/2013 08:58, Wanlong Gao ha scritto:
> > According to this patch set, we are able to set guest nodes memory policy
> > like following:
> > 
> >  -numa node,nodeid=0,cpus=0, \
> >  -numa mem,size=1024M,policy=membind,host-nodes=0-1 \
> >  -numa node,nodeid=1,cpus=1 \
> >  -numa mem,size=1024M,policy=interleave,host-nodes=1
> > 
> > This supports 
> > "policy={default|membind|interleave|preferred},relative=true,host-nodes=N-N"
> >  like format.
> > 
> > And add a QMP command "query-numa" to show numa info through
> > this API.
> 
> Marcelo, I'm afraid that these NUMA settings complicate getting properly
> aligned pages.  If you do something like this:
> 
>   -numa node,nodeid=0,cpus=0, \
>   -numa mem,size=4096M,policy=membind,host-nodes=0 \
>   -numa node,nodeid=1,cpus=1 \
>   -numa mem,size=4096M,policy=membind,host-nodes=1
> 
> You'll have with your patches (without them it's worse of course):
> 
>    RAM offset    physical address   node 0
>    0-3840M       0-3840M            host node 0
>    4096M-4352M   4096M-4352M        host node 0
>    4352M-8192M   4352M-8192M        host node 1
>    3840M-4096M   8192M-8448M        host node 1
> 
> So only 0-3G and 5-8G are aligned, 3G-5G and 8G-8.25G cannot use
> gigabyte pages because they are split across host nodes.

AFAIK the TLB caches virt->phys translations, why specifics of 
a given phys address is a factor into TLB caching?

> So rather than your patches, it seems simpler to just widen the PCI hole
> to 1G for i440FX and 2G for q35.
> 
> What do you think?

Problem is its a guest visible change. To get 1GB TLB entries with
"legacy guest visible machine types" (which require new machine types
at the host side, but invisible to guest), that won't work.
Windows registration invalidation etc.

But for q35, sure.