[Qemu-devel] [PATCH v2 2/3] X86, mpx: Intel MPX CPU feature definition

[Qiaowei Ren]

This patch defines Intel MPX CPU feature.

Signed-off-by: Qiaowei Ren <address@hidden>
Signed-off-by: Xudong Hao <address@hidden>
Signed-off-by: Liu Jinsong <address@hidden>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h 
b/arch/x86/include/asm/cpufeature.h
index d3f5c63..ef9f9c2 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -216,6 +216,7 @@
 #define X86_FEATURE_ERMS       (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
 #define X86_FEATURE_INVPCID    (9*32+10) /* Invalidate Processor Context ID */
 #define X86_FEATURE_RTM                (9*32+11) /* Restricted Transactional 
Memory */
+#define X86_FEATURE_MPX                (9*32+14) /* Memory Protection 
Extension */
 #define X86_FEATURE_RDSEED     (9*32+18) /* The RDSEED instruction */
 #define X86_FEATURE_ADX                (9*32+19) /* The ADCX and ADOX 
instructions */
 #define X86_FEATURE_SMAP       (9*32+20) /* Supervisor Mode Access Prevention 
*/
-- 
1.7.1