[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 00/13] target-arm: A64 decoder set 2: misc logic
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 00/13] target-arm: A64 decoder set 2: misc logic and bit ops |
Date: |
Fri, 6 Dec 2013 13:19:00 +0000 |
Second revision of the second chunk of A64 decoder patches:
a grabbag of miscellaneous logic and bit-twiddling operations,
plus some other minor stuff like ADR and conditional-select.
Changes v1->v2:
* added a couple of OPTME comments as suggested by RTH
* lowercased stray TRUE/FALSE
* in logical (shifted reg), use andc/orc/eqv rather than
explicit not, and special case MOV/MVN
* improve cond select code as suggested by RTH (but not
attempting any grander reworking of arm_gen_test_cc just yet)
NB: only patches 1 and 2 still need review :-)
Git tree (with v7-cpu-host/mach-virt, v8 kvm control,
and A64 set one all underneath these ptaches):
git://git.linaro.org/people/pmaydell/qemu-arm.git a64-second-set
web UI:
https://git.linaro.org/gitweb?p=people/pmaydell/qemu-arm.git;a=shortlog;h=refs/heads/a64-second-set
thanks
-- PMM
Alexander Graf (7):
target-arm: A64: add support for logical (shifted register)
target-arm: A64: add support for ADR and ADRP
target-arm: A64: add support for EXTR
target-arm: A64: add support for 2-src data processing and DIV
target-arm: A64: add support for 2-src shift reg insns
target-arm: A64: add support for 1-src RBIT insn
target-arm: A64: add support for logical (immediate) insns
Claudio Fontana (6):
target-arm: A64: add support for conditional select
target-arm: A64: add support for 1-src data processing and CLZ
target-arm: A64: add support for 1-src REV insns
target-arm: A64: add support for bitfield insns
host-utils: add clrsb32/64 - count leading redundant sign bits
target-arm: A64: add support for 1-src CLS insn
include/qemu/host-utils.h | 32 ++
target-arm/helper-a64.c | 54 +++
target-arm/helper-a64.h | 6 +
target-arm/translate-a64.c | 816 ++++++++++++++++++++++++++++++++++++++++++--
4 files changed, 888 insertions(+), 20 deletions(-)
--
1.7.9.5
- [Qemu-devel] [PATCH v2 00/13] target-arm: A64 decoder set 2: misc logic and bit ops,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 02/13] target-arm: A64: add support for logical (shifted register), Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 06/13] target-arm: A64: add support for 2-src shift reg insns, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 08/13] target-arm: A64: add support for 1-src RBIT insn, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 01/13] target-arm: A64: add support for conditional select, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 04/13] target-arm: A64: add support for EXTR, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 05/13] target-arm: A64: add support for 2-src data processing and DIV, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 09/13] target-arm: A64: add support for 1-src REV insns, Peter Maydell, 2013/12/06