Re: [Qemu-devel] [PATCH 14/60] AArch64: Add orr instruction emulation

[Michael Matz]

Hi,

On Mon, 18 Nov 2013, Claudio Fontana wrote:

> > +            tcg_gen_trunc_i64_i32(tmp, cpu_reg(reg));
> > +       tcg_gen_rotr_i32(tmp, tmp, tcg_shift);
> 
> Isn't this problematic?
> We are using gen_rotr_i32, but passing tcg_shift, which is a TCGv_i64.

With CONFIG_DEBUG_TCG it'll break, yes.  Though in principle there's no 
canonical relation between the two argument types for shifts and rotates 
(unlike addition for example) TCG indeed wants to ensure that 
typeof(arg2)==typeof(arg1).

> I remember I had compilation failures in the past when I tried something 
> similar, so my understanding is that this can work with a certain 
> compiler under certain compiler options, but is not guaranteed to work 
> in all cases.
> 
> I think we need to either explicitly convert the tcg_shift to a 
> TCGv_i32, or we need to use an open coded version of the rotr_i64 that 
> inserts at (32 - n) instead of (64 - n)
> 
> What do you think?

I think converting tcg_shift might eventually lead to better generated 
code (if tcg is optmizing enough, now or in the future, haven't checked).


Ciao,
Michael.