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[Qemu-devel] [PATCH for-1.8 51/61] target-i386: Remove gen_op_mov_reg_T0
|
From: |
Richard Henderson |
|
Subject: |
[Qemu-devel] [PATCH for-1.8 51/61] target-i386: Remove gen_op_mov_reg_T0 |
|
Date: |
Thu, 7 Nov 2013 11:05:14 +1000 |
Replace with its definition, via Coccinelle.
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/translate.c | 127 +++++++++++++++++++++++-------------------------
1 file changed, 61 insertions(+), 66 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index c663c6f..dd28d48 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -366,11 +366,6 @@ static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
}
}
-static inline void gen_op_mov_reg_T0(TCGMemOp ot, int reg)
-{
- gen_op_mov_reg_v(ot, reg, cpu_T[0]);
-}
-
static inline void gen_op_mov_reg_T1(TCGMemOp ot, int reg)
{
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
@@ -463,7 +458,7 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int
idx, int d)
if (d == OR_TMP0) {
gen_op_st_v(s, idx, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(idx, d);
+ gen_op_mov_reg_v(idx, d, cpu_T[0]);
}
}
@@ -1114,7 +1109,7 @@ static inline void gen_lods(DisasContext *s, TCGMemOp ot)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(ot, R_EAX);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
}
@@ -2075,11 +2070,11 @@ static void gen_ldst_modrm(CPUX86State *env,
DisasContext *s, int modrm,
if (is_store) {
if (reg != OR_TMP0)
gen_op_mov_TN_reg(ot, 0, reg);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
gen_op_mov_TN_reg(ot, 0, rm);
if (reg != OR_TMP0)
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
} else {
gen_lea_modrm(env, s, modrm);
@@ -2090,7 +2085,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext
*s, int modrm,
} else {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
if (reg != OR_TMP0)
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
}
}
@@ -2198,7 +2193,7 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext
*s, TCGMemOp ot, int b,
tcg_gen_movcond_tl(cc.cond, cpu_T[0], cc.reg, cc.reg2,
cpu_T[0], cpu_regs[reg]);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
if (cc.mask != -1) {
tcg_temp_free(cc.reg);
@@ -2350,7 +2345,7 @@ static void gen_popa(DisasContext *s)
tcg_gen_addi_tl(cpu_A0, cpu_regs[R_ESP], i * size);
gen_lea_v_seg(s, s_ot, cpu_A0, R_SS, -1);
gen_op_ld_v(s, d_ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(d_ot, 7 - i);
+ gen_op_mov_reg_v(d_ot, 7 - i, cpu_T[0]);
}
gen_stack_update(s, 8 * size);
@@ -3420,7 +3415,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
goto illegal_op;
#endif
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0xc4: /* pinsrw */
case 0x1c4:
@@ -3455,7 +3450,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
}
reg = ((modrm >> 3) & 7) | rex_r;
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x1d6: /* movq ea, xmm */
if (mod != 3) {
@@ -3606,7 +3601,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
cpu_T[0], tcg_const_i32(8 << ot));
ot = mo_64_32(s->dflag);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x1f0: /* crc32 or movbe */
@@ -3633,7 +3628,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
if ((b & 1) == 0) {
tcg_gen_qemu_ld_tl(cpu_T[0], cpu_A0,
s->mem_index, ot | MO_BE);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_regs[reg], cpu_A0,
s->mem_index, ot | MO_BE);
@@ -3649,7 +3644,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
ot = mo_64_32(s->dflag);
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
tcg_gen_andc_tl(cpu_T[0], cpu_regs[s->vex_v], cpu_T[0]);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
gen_op_update1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
break;
@@ -3688,7 +3683,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
tcg_gen_subi_tl(cpu_T[1], cpu_T[1], 1);
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
gen_op_update1_cc();
set_cc_op(s, CC_OP_LOGICB + ot);
}
@@ -3716,7 +3711,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
tcg_gen_movi_tl(cpu_A0, -1);
tcg_gen_shl_tl(cpu_A0, cpu_A0, cpu_T[1]);
tcg_gen_andc_tl(cpu_T[0], cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
gen_op_update1_cc();
set_cc_op(s, CC_OP_BMILGB + ot);
break;
@@ -3890,7 +3885,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
}
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x0f3:
@@ -3909,7 +3904,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
case 1: /* blsr By,Ey */
tcg_gen_neg_tl(cpu_T[1], cpu_T[0]);
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(ot, s->vex_v);
+ gen_op_mov_reg_v(ot, s->vex_v, cpu_T[0]);
gen_op_update2_cc();
set_cc_op(s, CC_OP_BMILGB + ot);
break;
@@ -3970,7 +3965,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
if (mod == 3) {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_UB);
@@ -3980,7 +3975,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_W(val & 7)));
if (mod == 3) {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_LEUW);
@@ -4017,7 +4012,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3)));
if (mod == 3) {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0,
s->mem_index, MO_LEUL);
@@ -4150,7 +4145,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, b & 31);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
default:
@@ -4475,7 +4470,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
/* xor reg, reg optimisation */
set_cc_op(s, CC_OP_CLR);
tcg_gen_movi_tl(cpu_T[0], 0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
} else {
opreg = rm;
@@ -4589,7 +4584,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
break;
case 3: /* neg */
@@ -4597,7 +4592,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
gen_op_update_neg_cc();
set_cc_op(s, CC_OP_SUBB + ot);
@@ -4610,7 +4605,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
set_cc_op(s, CC_OP_MULB);
@@ -4621,10 +4616,10 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
- gen_op_mov_reg_T0(MO_16, R_EDX);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
set_cc_op(s, CC_OP_MULW);
break;
@@ -4659,7 +4654,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
@@ -4671,12 +4666,12 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
- gen_op_mov_reg_T0(MO_16, R_EDX);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
set_cc_op(s, CC_OP_MULW);
break;
default:
@@ -4895,18 +4890,18 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
case MO_64:
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_64, R_EAX);
+ gen_op_mov_reg_v(MO_64, R_EAX, cpu_T[0]);
break;
#endif
case MO_32:
gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_32, R_EAX);
+ gen_op_mov_reg_v(MO_32, R_EAX, cpu_T[0]);
break;
case MO_16:
gen_op_mov_TN_reg(MO_8, 0, R_EAX);
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
break;
default:
tcg_abort();
@@ -4918,20 +4913,20 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
case MO_64:
gen_op_mov_TN_reg(MO_64, 0, R_EAX);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
- gen_op_mov_reg_T0(MO_64, R_EDX);
+ gen_op_mov_reg_v(MO_64, R_EDX, cpu_T[0]);
break;
#endif
case MO_32:
gen_op_mov_TN_reg(MO_32, 0, R_EAX);
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
- gen_op_mov_reg_T0(MO_32, R_EDX);
+ gen_op_mov_reg_v(MO_32, R_EDX, cpu_T[0]);
break;
case MO_16:
gen_op_mov_TN_reg(MO_16, 0, R_EAX);
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
- gen_op_mov_reg_T0(MO_16, R_EDX);
+ gen_op_mov_reg_v(MO_16, R_EDX, cpu_T[0]);
break;
default:
tcg_abort();
@@ -4985,7 +4980,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
}
set_cc_op(s, CC_OP_MULB + ot);
@@ -5002,7 +4997,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
gen_op_mov_TN_reg(ot, 1, rm);
gen_op_addl_T0_T1();
gen_op_mov_reg_T1(ot, reg);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_mov_TN_reg(ot, 0, reg);
@@ -5106,7 +5101,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
ot = gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
gen_pop_update(s, ot);
- gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
+ gen_op_mov_reg_v(ot, (b & 7) | REX_B(s), cpu_T[0]);
break;
case 0x60: /* pusha */
if (CODE64(s))
@@ -5136,7 +5131,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
/* NOTE: order is important for pop %sp */
gen_pop_update(s, ot);
rm = (modrm & 7) | REX_B(s);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else {
/* NOTE: order is important too for MMU exceptions */
s->popl_esp_hack = 1 << ot;
@@ -5229,7 +5224,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
+ gen_op_mov_reg_v(ot, (modrm & 7) | REX_B(s), cpu_T[0]);
}
break;
case 0x8a:
@@ -5239,7 +5234,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
reg = ((modrm >> 3) & 7) | rex_r;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
case 0x8e: /* mov seg, Gv */
modrm = cpu_ldub_code(env, s->pc++);
@@ -5309,11 +5304,11 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
break;
}
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, s_ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
}
}
break;
@@ -5357,7 +5352,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
gen_op_ld_v(s, ot, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(ot, R_EAX);
+ gen_op_mov_reg_v(ot, R_EAX, cpu_T[0]);
} else {
gen_op_mov_TN_reg(ot, 0, R_EAX);
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
@@ -5371,12 +5366,12 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
gen_extu(s->aflag, cpu_A0);
gen_add_A0_ds_seg(s);
gen_op_ld_v(s, MO_8, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(MO_8, R_EAX);
+ gen_op_mov_reg_v(MO_8, R_EAX, cpu_T[0]);
break;
case 0xb0 ... 0xb7: /* mov R, Ib */
val = insn_get(env, s, MO_8);
tcg_gen_movi_tl(cpu_T[0], val);
- gen_op_mov_reg_T0(MO_8, (b & 7) | REX_B(s));
+ gen_op_mov_reg_v(MO_8, (b & 7) | REX_B(s), cpu_T[0]);
break;
case 0xb8 ... 0xbf: /* mov R, Iv */
#ifdef TARGET_X86_64
@@ -5387,7 +5382,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
s->pc += 8;
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(cpu_T[0], tmp);
- gen_op_mov_reg_T0(MO_64, reg);
+ gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
} else
#endif
{
@@ -5395,7 +5390,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
val = insn_get(env, s, ot);
reg = (b & 7) | REX_B(s);
tcg_gen_movi_tl(cpu_T[0], val);
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
break;
@@ -5416,7 +5411,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
do_xchg_reg:
gen_op_mov_TN_reg(ot, 0, reg);
gen_op_mov_TN_reg(ot, 1, rm);
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
gen_op_mov_reg_T1(ot, reg);
} else {
gen_lea_modrm(env, s, modrm);
@@ -6019,7 +6014,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
case 0:
gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
- gen_op_mov_reg_T0(MO_16, R_EAX);
+ gen_op_mov_reg_v(MO_16, R_EAX, cpu_T[0]);
break;
default:
goto illegal_op;
@@ -6483,7 +6478,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
gen_compute_eflags(s);
/* Note: gen_compute_eflags() only gives the condition codes */
tcg_gen_ori_tl(cpu_T[0], cpu_cc_src, 0x02);
- gen_op_mov_reg_T0(MO_8, R_AH);
+ gen_op_mov_reg_v(MO_8, R_AH, cpu_T[0]);
break;
case 0xf5: /* cmc */
gen_compute_eflags(s);
@@ -6590,7 +6585,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
if (mod != 3) {
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
} else {
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
tcg_gen_movi_tl(cpu_cc_dst, 0);
@@ -6647,7 +6642,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_T[0], cpu_cc_dst, cpu_tmp0,
cpu_regs[reg], cpu_T[0]);
}
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
break;
/************************/
/* bcd */
@@ -6816,14 +6811,14 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
if (dflag == MO_64) {
gen_op_mov_TN_reg(MO_64, 0, reg);
tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_64, reg);
+ gen_op_mov_reg_v(MO_64, reg, cpu_T[0]);
} else
#endif
{
gen_op_mov_TN_reg(MO_32, 0, reg);
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_32, reg);
+ gen_op_mov_reg_v(MO_32, reg, cpu_T[0]);
}
break;
case 0xd6: /* salc */
@@ -6831,7 +6826,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
goto illegal_op;
gen_compute_eflags_c(s, cpu_T[0]);
tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(MO_8, R_EAX);
+ gen_op_mov_reg_v(MO_8, R_EAX, cpu_T[0]);
break;
case 0xe0: /* loopnz */
case 0xe1: /* loopz */
@@ -7317,11 +7312,11 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
/* sign extend */
if (d_ot == MO_64)
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
} else {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0);
- gen_op_mov_reg_T0(d_ot, reg);
+ gen_op_mov_reg_v(d_ot, reg, cpu_T[0]);
}
} else
#endif
@@ -7459,7 +7454,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
gen_eob(s);
} else {
gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg));
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
break;
default:
@@ -7496,7 +7491,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
tcg_gen_ld_tl(cpu_T[0], cpu_env,
offsetof(CPUX86State,dr[reg]));
- gen_op_mov_reg_T0(ot, rm);
+ gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
}
break;
@@ -7631,7 +7626,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
- gen_op_mov_reg_T0(ot, reg);
+ gen_op_mov_reg_v(ot, reg, cpu_T[0]);
set_cc_op(s, CC_OP_EFLAGS);
break;
--
1.8.3.1
- [Qemu-devel] [PATCH for-1.8 39/61] target-i386: Tidy addr16 code in gen_lea_modrm, (continued)
- [Qemu-devel] [PATCH for-1.8 39/61] target-i386: Tidy addr16 code in gen_lea_modrm, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 40/61] target-i386: Combine gen_push_T* into gen_push_v, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 41/61] target_i386: Clean up gen_pop_T0, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 42/61] target-i386: Create gen_lea_v_seg, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 43/61] target-i386: Use gen_lea_v_seg in gen_lea_modrm, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 44/61] target-i386: Use gen_lea_v_seg in stack subroutines, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 45/61] target-i386: Tidy cpu_regs initialization, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 46/61] target-i386: Access segs via TCG registers, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 49/61] target-i386: Introduce mo_stacksize, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 50/61] target-i386: Rewrite leave, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 51/61] target-i386: Remove gen_op_mov_reg_T0,
Richard Henderson <=
- [Qemu-devel] [PATCH for-1.8 52/61] target-i386: Remove gen_op_mov_reg_T1, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 53/61] target-i386: Remove gen_op_addl_T0_T1, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 55/61] target-i386: Remove gen_op_mov_reg_A0, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 56/61] target-i386: Remove gen_op_movl_A0_reg, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 54/61] target-i386: Remove gen_op_mov_TN_reg, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 57/61] target-i386: Tidy gen_add_A0_im, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 58/61] target-i386: Tidy some size computation, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 59/61] target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 60/61] target-i386: Tidy ljmp, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 47/61] target-i386: Use gen_lea_v_seg in pusha/popa, Richard Henderson, 2013/11/06