Re: [Qemu-devel] [PATCH 00/60] AArch64 TCG emulation support

[Edgar E. Iglesias]

On Fri, Sep 27, 2013 at 02:47:54AM +0200, Alexander Graf wrote:
> Howdy,
> 
> This is the first batch of patches to implement AArch64 instruction
> emulation in QEMU. It implements enough to execute simple AArch64
> programs in linux-user mode.
> 
> We still have quite a big number of patches outstanding that will
> come after this initial set, both in linux-user code as well as in
> the AArch64 instruction emulator. But this series is already quite
> big, so let's get this one through first.


Impressive work Alex!

It would be fun to try this out, do you have a public repo with these
patches?
How much progress have you made on system emulation?

Best regards,
Edgar



> 
> If you need a rootfs to try this out on, I recommend using our openSUSE
> 12.3 tarball:
> 
>   http://download.opensuse.org/repositories/devel:/ARM:/AArch64:/12.3/images/
> 
> 
> Alex
> 
> Alexander Graf (60):
>   arm: Use symbolic device names for vfp cmp
>   arm: Give the fpscr rounding modes names
>   arm: Split VFP cmp from FPSCR setting
>   arm: Add AArch64 disassembler stub
>   softfloat: Add stubs for int16 conversion
>   AArch64: Add set_pc cpu method
>   ARM: Add 64bit VFP handling
>   AArch64: Add support to print VFP registers in CPU dump
>   AArch64: Add b and bl handling
>   AArch64: Add handling for br instructions
>   AArch64: Add STP instruction emulation
>   AArch64: Add ldarx style instruction emulation
>   AArch64: Add stubs for a64 specific helpers
>   AArch64: Add orr instruction emulation
>   AArch64: Add add instruction family emulation
>   AArch64: Add emulation for SIMD ld/st multiple
>   AArch64: Add dup GPR->Vec instruction emulation
>   AArch64: Add umov instruction emulation
>   AArch64: Add ins GPR->Vec instruction emulation
>   AArch64: Add SIMD ORR family instruction emulation
>   AArch64: Convert SIMD load/store to common function
>   AArch64: Add AdvSIMD scalar three same group handling
>   AArch64: Add AdvSIMD modified immediate group handling
>   AArch64: Add SIMD ushll instruction emulation
>   AArch64: Add SIMD shl instruction emulation
>   AArch64: Add ADR instruction emulation
>   AArch64: Add addi instruction emulation
>   AArch64: Add movi instruction emulation
>   AArch64: Add orri instruction emulation
>   AArch64: Add extr instruction emulation
>   AArch64: Add bfm family instruction emulation
>   AArch64: Add svc instruction emulation
>   AArch64: Add bc instruction emulation
>   AArch64: Add b.cond instruction emulation
>   AArch64: Add mrs instruction emulation
>   AArch64: Add msr instruction emulation
>   AArch64: Add hint instruction emulation
>   AArch64: Add stub barrier instruction emulation
>   AArch64: Add stub sys instruction emulation
>   AArch64: Add tbz instruction emulation
>   AArch64: Add ldr/str instruction family emulation
>   AArch64: Add literal ld instruction emulation
>   AArch64: Add cinc instruction emulation
>   AArch64: Add division instruction family emulation
>   AArch64: Add shift instruction family emulation
>   AArch64: Add rev instruction family emulation
>   AArch64: Add clz instruction emulation
>   AArch64: Add 0x1a encoding of add instructions
>   AArch64: Add "Data-processing (3 source)" instruction family
>     emulation
>   AArch64: Add "Floating-point<->fixed-point conversions" category
>     emulation
>   AArch64: Add fmov (scalar, immediate) instruction emulation
>   AArch64: Add "Floating-point<->integer conversions" instruction
>     family emulation
>   AArch64: Add "Floating-point compare" instruction family emulation
>   AArch64: Add "Floating-point data-processing (1 source)" (32 bit)
>     instruction family emulation
>   AArch64: Add "Floating-point data-processing (1 source)" (64 bit)
>     instruction family emulation
>   AArch64: Add "Floating-point data-processing (2 source)" (32 bit)
>     instruction family emulation
>   AArch64: Add "Floating-point data-processing (2 source)" (64 bit)
>     instruction family emulation
>   AArch64: Add "ADD (vector)" instruction emulation
>   AArch64: Add "Floating-point data-processing (3 source)" (32 bit)
>     instruction family emulation
>   AArch64: Add "Floating-point data-processing (3 source)" (64 bit)
>     instruction family emulation
> 
>  disas.c                    |    6 +-
>  disas/Makefile.objs        |    1 +
>  disas/aarch64.c            |   31 +
>  fpu/softfloat.c            |   21 +
>  include/disas/bfd.h        |    1 +
>  include/fpu/softfloat.h    |    4 +
>  target-arm/Makefile.objs   |    2 +-
>  target-arm/cpu.h           |    5 +
>  target-arm/cpu64.c         |    8 +
>  target-arm/helper-a64.c    |  309 +++++
>  target-arm/helper-a64.h    |   35 +
>  target-arm/helper.c        |  108 +-
>  target-arm/helper.h        |   24 +-
>  target-arm/translate-a64.c | 2915 
> +++++++++++++++++++++++++++++++++++++++++++-
>  target-arm/translate.c     |   13 +-
>  target-arm/translate.h     |    5 +
>  16 files changed, 3424 insertions(+), 64 deletions(-)
>  create mode 100644 disas/aarch64.c
>  create mode 100644 target-arm/helper-a64.c
>  create mode 100644 target-arm/helper-a64.h
> 
> -- 
> 1.7.12.4
> 
>