[Qemu-devel] [PATCH 47/60] AArch64: Add clz instruction emulation

[Alexander Graf]

This patch adds emlulation support for the clz instruction.

Signed-off-by: Alexander Graf <address@hidden>
---
 target-arm/helper-a64.c    |  5 +++++
 target-arm/helper-a64.h    |  1 +
 target-arm/translate-a64.c | 31 +++++++++++++++++++++++++++++++
 3 files changed, 37 insertions(+)

diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index e20b89f..a8a8499 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -256,3 +256,8 @@ uint64_t HELPER(rbit64)(uint64_t x)
        | ((x & 0x1111111111111111ULL) << 3);
     return x;
 }
+
+uint64_t HELPER(clz64)(uint64_t x)
+{
+    return clz64(x);
+}
diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h
index 5e5cda0..607ba8a 100644
--- a/target-arm/helper-a64.h
+++ b/target-arm/helper-a64.h
@@ -27,3 +27,4 @@ DEF_HELPER_FLAGS_4(cinc, TCG_CALL_NO_RWG_SE, i64, i32, i32, 
i64, i64)
 DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
 DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(clz64, TCG_CALL_NO_RWG_SE, i64, i64)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 208d06b..db55389 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1602,6 +1602,35 @@ static void handle_rev(DisasContext *s, uint32_t insn)
     }
 }
 
+static void handle_clz(DisasContext *s, uint32_t insn)
+{
+    int rd = get_reg(insn);
+    int rn = get_bits(insn, 5, 5);
+    int opc = get_bits(insn, 10, 2);
+    bool is_32bit = !get_bits(insn, 31, 1);
+    TCGv_i64 tcg_val = tcg_temp_new_i64();
+
+    if (is_32bit) {
+        tcg_gen_ext32u_i64(tcg_val, cpu_reg(rn));
+    } else {
+        tcg_gen_mov_i64(tcg_val, cpu_reg(rn));
+    }
+
+    switch (opc) {
+    case 0x0: /* CLZ */
+        gen_helper_clz64(cpu_reg(rd), tcg_val);
+        if (is_32bit) {
+            tcg_gen_subi_i64(cpu_reg(rd), cpu_reg(rd), 32);
+        }
+        break;
+    case 0x1: /* CLS */
+        unallocated_encoding(s);
+        break;
+    }
+
+    tcg_temp_free_i64(tcg_val);
+}
+
 /* SIMD ORR */
 static void handle_simdorr(DisasContext *s, uint32_t insn)
 {
@@ -2170,6 +2199,8 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s)
             handle_shift_reg(s, insn);
         } else if ((insn & 0x7ffff000) == 0x5ac00000) {
             handle_rev(s, insn);
+        } else if ((insn & 0x7ffff800) == 0x5ac01000) {
+            handle_clz(s, insn);
         } else {
             unallocated_encoding(s);
         }
-- 
1.7.12.4