[Qemu-devel] [PATCH 32/60] AArch64: Add svc instruction emulation

[Alexander Graf]

This patch adds emulation for the syscall (svc) instruction.

Signed-off-by: Alexander Graf <address@hidden>
---
 target-arm/translate-a64.c | 13 +++++++++++++
 target-arm/translate.c     |  5 -----
 target-arm/translate.h     |  5 +++++
 3 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 583a68f..fdcf876 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1583,6 +1583,12 @@ static void handle_simdshl(DisasContext *s, uint32_t 
insn)
     tcg_temp_free_i64(tcg_tmp);
 }
 
+static void handle_svc(DisasContext *s, uint32_t insn)
+{
+    gen_a64_set_pc_im(s->pc);
+    s->is_jmp = DISAS_SWI;
+}
+
 void disas_a64_insn(CPUARMState *env, DisasContext *s)
 {
     uint32_t insn;
@@ -1697,6 +1703,13 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s)
             handle_bfm(s, insn);
         }
         break;
+    case 0x14:
+        if (get_bits(insn, 29, 3) == 0x6 && !get_bits(insn, 2, 3)) {
+            handle_svc(s, insn);
+        } else {
+            unallocated_encoding(s);
+        }
+        break;
     default:
         unallocated_encoding(s);
         break;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index ef284da..8d75f33 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -55,11 +55,6 @@ static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
 #define IS_USER(s) (s->user)
 #endif
 
-/* These instructions trap after executing, so defer them until after the
-   conditional execution state has been updated.  */
-#define DISAS_WFI 4
-#define DISAS_SWI 5
-
 TCGv_ptr cpu_env;
 /* We reuse the same 64-bit temporaries for efficiency.  */
 static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 67c7760..bc21741 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -1,6 +1,11 @@
 #ifndef TARGET_ARM_TRANSLATE_H
 #define TARGET_ARM_TRANSLATE_H
 
+/* These instructions trap after executing, so defer them until after the
+   conditional execution state has been updated.  */
+#define DISAS_WFI 4
+#define DISAS_SWI 5
+
 /* internal defines */
 typedef struct DisasContext {
     target_ulong pc;
-- 
1.7.12.4