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[Qemu-devel] [PATCH v4 10/33] tcg-aarch64: Implement mov with tcg_fmt_*
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 10/33] tcg-aarch64: Implement mov with tcg_fmt_* functions |
Date: |
Sat, 14 Sep 2013 14:54:27 -0700 |
Avoid the magic numbers in the current implementation.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/aarch64/tcg-target.c | 24 ++++++++++--------------
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 56625a9..93badfd 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -379,13 +379,18 @@ static inline void tcg_out_ldst_12(TCGContext *s,
| op_type << 20 | scaled_uimm << 10 | rn << 5 | rd);
}
+/* Register to register move using ORR (shifted register with no shift). */
static inline void tcg_out_movr(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg src)
+ TCGReg rd, TCGReg rm)
{
- /* register to register move using MOV (shifted register with no shift) */
- /* using MOV 0x2a0003e0 | (shift).. */
- unsigned int base = ext ? 0xaa0003e0 : 0x2a0003e0;
- tcg_out32(s, base | src << 16 | rd);
+ tcg_fmt_Rdnm(s, INSN_ORR, ext, rd, TCG_REG_XZR, rm);
+}
+
+/* Register to register move using ADDI (move to/from SP). */
+static inline void tcg_out_movr_sp(TCGContext *s, TCGType ext,
+ TCGReg rd, TCGReg rn)
+{
+ tcg_fmt_Rdn_aimm(s, INSN_ADDI, ext, rd, rn, 0);
}
static inline void tcg_out_movi_aux(TCGContext *s,
@@ -460,15 +465,6 @@ static inline void tcg_out_ldst(TCGContext *s, enum
aarch64_ldst_op_data data,
tcg_out_ldst_r(s, data, type, rd, rn, TCG_REG_TMP);
}
-/* mov alias implemented with add immediate, useful to move to/from SP */
-static inline void tcg_out_movr_sp(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rn)
-{
- /* using ADD 0x11000000 | (ext) | rn << 5 | rd */
- unsigned int base = ext ? 0x91000000 : 0x11000000;
- tcg_out32(s, base | rn << 5 | rd);
-}
-
static inline void tcg_out_mov(TCGContext *s,
TCGType type, TCGReg ret, TCGReg arg)
{
--
1.8.3.1
[Qemu-devel] [PATCH v4 12/33] tcg-aarch64: Handle constant operands to and, or, xor, Richard Henderson, 2013/09/14
[Qemu-devel] [PATCH v4 13/33] tcg-aarch64: Support andc, orc, eqv, not, Richard Henderson, 2013/09/14
[Qemu-devel] [PATCH v4 14/33] tcg-aarch64: Handle zero as first argument to sub, Richard Henderson, 2013/09/14
[Qemu-devel] [PATCH v4 15/33] tcg-aarch64: Support movcond, Richard Henderson, 2013/09/14
[Qemu-devel] [PATCH v4 16/33] tcg-aarch64: Use tcg_fmt_Rdnm_cond for setcond, Richard Henderson, 2013/09/14