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Re: [Qemu-devel] [PATCH RFC v2 2/2] hw/pci: handle unassigned pci addres

From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH RFC v2 2/2] hw/pci: handle unassigned pci addresses
Date: Mon, 9 Sep 2013 17:02:15 +0100

On 9 September 2013 17:00, Michael S. Tsirkin <address@hidden> wrote:
> On Mon, Sep 09, 2013 at 03:58:36PM +0100, Peter Maydell wrote:
>> On 9 September 2013 15:51, Marcel Apfelbaum <address@hidden> wrote:
>> > On Mon, 2013-09-09 at 15:21 +0100, Peter Maydell wrote:
>> >> No, it's perfectly possible for a bus master transaction
>> >> to abort. The PC's host controller happens to be set up so
>> >> that bus master DMA covers the whole of the PCI memory space
>> >> and so it's probably not possible to get an abort on that
>> >> platform, but this isn't necessarily the case. For instance
>> >> the versatilePB's PCI controller only responds to accesses
>> >> within its programmed MMIO BAR ranges, so if the device
>> >> or the controller have been misconfigured you can get an
>> >> abort when the device tries to do DMA. (This usually causes
>> >> the device to decide something has gone seriously wrong.
>> > Thanks, I am not familiar with versatilePB, I may be able
>> > to code it, I don't know how to test it
>> Don't worry about testing versatilePB particularly; you
>> just need to make sure your code can cope with master
>> aborts by device initiated transactions.
> Device in question being PCI host right?

No, in the scenario described above the device doing the write
and getting the abort is the EHCI USB controller.

-- PMM

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