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[Qemu-devel] [PATCH 05/16] tcg-s390: Use TCGMemOp within qemu_ldst routi
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 05/16] tcg-s390: Use TCGMemOp within qemu_ldst routines |
Date: |
Wed, 4 Sep 2013 14:04:54 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/s390/tcg-target.c | 107 ++++++++++++++++++++++----------------------------
1 file changed, 46 insertions(+), 61 deletions(-)
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 1b44aee..e640f86 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -224,16 +224,6 @@ typedef enum S390Opcode {
RX_STH = 0x40,
} S390Opcode;
-#define LD_SIGNED 0x04
-#define LD_UINT8 0x00
-#define LD_INT8 (LD_UINT8 | LD_SIGNED)
-#define LD_UINT16 0x01
-#define LD_INT16 (LD_UINT16 | LD_SIGNED)
-#define LD_UINT32 0x02
-#define LD_INT32 (LD_UINT32 | LD_SIGNED)
-#define LD_UINT64 0x03
-#define LD_INT64 (LD_UINT64 | LD_SIGNED)
-
#ifndef NDEBUG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
@@ -1284,22 +1274,19 @@ static void tgen_calli(TCGContext *s, tcg_target_long
dest)
}
}
-static void tcg_out_qemu_ld_direct(TCGContext *s, int opc, TCGReg data,
+static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
TCGReg base, TCGReg index, int disp)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- const int bswap = 0;
-#else
- const int bswap = 1;
-#endif
- switch (opc) {
- case LD_UINT8:
+ const TCGMemOp bswap = opc & MO_BSWAP;
+
+ switch (opc & MO_SSIZE) {
+ case MO_UB:
tcg_out_insn(s, RXY, LLGC, data, base, index, disp);
break;
- case LD_INT8:
+ case MO_SB:
tcg_out_insn(s, RXY, LGB, data, base, index, disp);
break;
- case LD_UINT16:
+ case MO_UW:
if (bswap) {
/* swapped unsigned halfword load with upper bits zeroed */
tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
@@ -1308,7 +1295,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int
opc, TCGReg data,
tcg_out_insn(s, RXY, LLGH, data, base, index, disp);
}
break;
- case LD_INT16:
+ case MO_SW:
if (bswap) {
/* swapped sign-extended halfword load */
tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
@@ -1317,7 +1304,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int
opc, TCGReg data,
tcg_out_insn(s, RXY, LGH, data, base, index, disp);
}
break;
- case LD_UINT32:
+ case MO_UL:
if (bswap) {
/* swapped unsigned int load with upper bits zeroed */
tcg_out_insn(s, RXY, LRV, data, base, index, disp);
@@ -1326,7 +1313,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int
opc, TCGReg data,
tcg_out_insn(s, RXY, LLGF, data, base, index, disp);
}
break;
- case LD_INT32:
+ case MO_SL:
if (bswap) {
/* swapped sign-extended int load */
tcg_out_insn(s, RXY, LRV, data, base, index, disp);
@@ -1335,7 +1322,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int
opc, TCGReg data,
tcg_out_insn(s, RXY, LGF, data, base, index, disp);
}
break;
- case LD_UINT64:
+ case MO_Q:
if (bswap) {
tcg_out_insn(s, RXY, LRVG, data, base, index, disp);
} else {
@@ -1347,23 +1334,20 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int
opc, TCGReg data,
}
}
-static void tcg_out_qemu_st_direct(TCGContext *s, int opc, TCGReg data,
+static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
TCGReg base, TCGReg index, int disp)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- const int bswap = 0;
-#else
- const int bswap = 1;
-#endif
- switch (opc) {
- case LD_UINT8:
+ const TCGMemOp bswap = opc & MO_BSWAP;
+
+ switch (opc & MO_SIZE) {
+ case MO_8:
if (disp >= 0 && disp < 0x1000) {
tcg_out_insn(s, RX, STC, data, base, index, disp);
} else {
tcg_out_insn(s, RXY, STCY, data, base, index, disp);
}
break;
- case LD_UINT16:
+ case MO_16:
if (bswap) {
tcg_out_insn(s, RXY, STRVH, data, base, index, disp);
} else if (disp >= 0 && disp < 0x1000) {
@@ -1372,7 +1356,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int
opc, TCGReg data,
tcg_out_insn(s, RXY, STHY, data, base, index, disp);
}
break;
- case LD_UINT32:
+ case MO_32:
if (bswap) {
tcg_out_insn(s, RXY, STRV, data, base, index, disp);
} else if (disp >= 0 && disp < 0x1000) {
@@ -1381,7 +1365,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int
opc, TCGReg data,
tcg_out_insn(s, RXY, STY, data, base, index, disp);
}
break;
- case LD_UINT64:
+ case MO_64:
if (bswap) {
tcg_out_insn(s, RXY, STRVG, data, base, index, disp);
} else {
@@ -1395,14 +1379,15 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int
opc, TCGReg data,
#if defined(CONFIG_SOFTMMU)
static TCGReg tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
- TCGReg addr_reg, int mem_index, int opc,
- uint16_t **label2_ptr_p, int is_store)
+ TCGReg addr_reg, int mem_index,
+ TCGMemOp opc, uint16_t **label2_ptr_p,
+ int is_store)
{
const TCGReg arg0 = tcg_target_call_iarg_regs[0];
const TCGReg arg1 = tcg_target_call_iarg_regs[1];
const TCGReg arg2 = tcg_target_call_iarg_regs[2];
const TCGReg arg3 = tcg_target_call_iarg_regs[3];
- int s_bits = opc & 3;
+ TCGMemOp s_bits = opc & MO_SIZE;
uint16_t *label1_ptr;
tcg_target_long ofs;
@@ -1446,17 +1431,17 @@ static TCGReg tcg_prepare_qemu_ldst(TCGContext* s,
TCGReg data_reg,
if (is_store) {
/* Make sure to zero-extend the value to the full register
for the calling convention. */
- switch (opc) {
- case LD_UINT8:
+ switch (opc & MO_SIZE) {
+ case MO_8:
tgen_ext8u(s, TCG_TYPE_I64, arg2, data_reg);
break;
- case LD_UINT16:
+ case MO_16:
tgen_ext16u(s, TCG_TYPE_I64, arg2, data_reg);
break;
- case LD_UINT32:
+ case MO_32:
tgen_ext32u(s, arg2, data_reg);
break;
- case LD_UINT64:
+ case MO_64:
tcg_out_mov(s, TCG_TYPE_I64, arg2, data_reg);
break;
default:
@@ -1471,14 +1456,14 @@ static TCGReg tcg_prepare_qemu_ldst(TCGContext* s,
TCGReg data_reg,
tgen_calli(s, (tcg_target_ulong)qemu_ld_helpers[s_bits]);
/* sign extension */
- switch (opc) {
- case LD_INT8:
+ switch (opc & MO_SSIZE) {
+ case MO_SB:
tgen_ext8s(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
break;
- case LD_INT16:
+ case MO_SW:
tgen_ext16s(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
break;
- case LD_INT32:
+ case MO_SL:
tgen_ext32s(s, data_reg, TCG_REG_R2);
break;
default:
@@ -1531,7 +1516,7 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGReg
*addr_reg,
/* load data with address translation (if applicable)
and endianness conversion */
-static void tcg_out_qemu_ld(TCGContext* s, const TCGArg* args, int opc)
+static void tcg_out_qemu_ld(TCGContext* s, const TCGArg* args, TCGMemOp opc)
{
TCGReg addr_reg, data_reg;
#if defined(CONFIG_SOFTMMU)
@@ -1560,7 +1545,7 @@ static void tcg_out_qemu_ld(TCGContext* s, const TCGArg*
args, int opc)
#endif
}
-static void tcg_out_qemu_st(TCGContext* s, const TCGArg* args, int opc)
+static void tcg_out_qemu_st(TCGContext* s, const TCGArg* args, TCGMemOp opc)
{
TCGReg addr_reg, data_reg;
#if defined(CONFIG_SOFTMMU)
@@ -1833,36 +1818,36 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
break;
case INDEX_op_qemu_ld8u:
- tcg_out_qemu_ld(s, args, LD_UINT8);
+ tcg_out_qemu_ld(s, args, MO_UB);
break;
case INDEX_op_qemu_ld8s:
- tcg_out_qemu_ld(s, args, LD_INT8);
+ tcg_out_qemu_ld(s, args, MO_SB);
break;
case INDEX_op_qemu_ld16u:
- tcg_out_qemu_ld(s, args, LD_UINT16);
+ tcg_out_qemu_ld(s, args, MO_TEUW);
break;
case INDEX_op_qemu_ld16s:
- tcg_out_qemu_ld(s, args, LD_INT16);
+ tcg_out_qemu_ld(s, args, MO_TESW);
break;
case INDEX_op_qemu_ld32:
/* ??? Technically we can use a non-extending instruction. */
- tcg_out_qemu_ld(s, args, LD_UINT32);
+ tcg_out_qemu_ld(s, args, MO_TEUL);
break;
case INDEX_op_qemu_ld64:
- tcg_out_qemu_ld(s, args, LD_UINT64);
+ tcg_out_qemu_ld(s, args, MO_TEQ);
break;
case INDEX_op_qemu_st8:
- tcg_out_qemu_st(s, args, LD_UINT8);
+ tcg_out_qemu_st(s, args, MO_UB);
break;
case INDEX_op_qemu_st16:
- tcg_out_qemu_st(s, args, LD_UINT16);
+ tcg_out_qemu_st(s, args, MO_TEUW);
break;
case INDEX_op_qemu_st32:
- tcg_out_qemu_st(s, args, LD_UINT32);
+ tcg_out_qemu_st(s, args, MO_TEUL);
break;
case INDEX_op_qemu_st64:
- tcg_out_qemu_st(s, args, LD_UINT64);
+ tcg_out_qemu_st(s, args, MO_TEQ);
break;
case INDEX_op_mov_i64:
@@ -2066,10 +2051,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
break;
case INDEX_op_qemu_ld32u:
- tcg_out_qemu_ld(s, args, LD_UINT32);
+ tcg_out_qemu_ld(s, args, MO_TEUL);
break;
case INDEX_op_qemu_ld32s:
- tcg_out_qemu_ld(s, args, LD_INT32);
+ tcg_out_qemu_ld(s, args, MO_TESL);
break;
OP_32_64(deposit):
--
1.8.1.4
- [Qemu-devel] [PATCH 00/16] Streamlining endian handling in TCG, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 03/16] tcg-aarch64: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 04/16] tcg-arm: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 02/16] tcg-i386: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 01/16] tcg: Add TCGMemOp, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 05/16] tcg-s390: Use TCGMemOp within qemu_ldst routines,
Richard Henderson <=
- [Qemu-devel] [PATCH 06/16] tcg-ppc: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 07/16] tcg-ppc64: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 08/16] tcg-hppa: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 09/16] tcg-mips: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 10/16] tcg-sparc: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 11/16] tcg: Add qemu_ld_st_i32/64, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 12/16] exec: Add both big- and little-endian memory helpers, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 14/16] tcg-i386: Remove "cb" output restriction from qemu_st8 for i386, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 13/16] tcg-i386: Tidy softmmu routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 15/16] tcg-i386: Support new ldst opcodes, Richard Henderson, 2013/09/04