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[Qemu-devel] [PULL 02/29] tcg-mips: Implement mulsh, muluh
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 02/29] tcg-mips: Implement mulsh, muluh |
Date: |
Mon, 2 Sep 2013 09:28:47 -0700 |
With the optimization in tcg_liveness_analysis,
we can avoid the MFLO when it is unused.
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/mips/tcg-target.c | 10 ++++++++++
tcg/mips/tcg-target.h | 4 ++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 793532e..31cd514 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -1423,6 +1423,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);
tcg_out_opc_reg(s, OPC_MFHI, args[1], 0, 0);
break;
+ case INDEX_op_mulsh_i32:
+ tcg_out_opc_reg(s, OPC_MULT, 0, args[1], args[2]);
+ tcg_out_opc_reg(s, OPC_MFHI, args[0], 0, 0);
+ break;
+ case INDEX_op_muluh_i32:
+ tcg_out_opc_reg(s, OPC_MULTU, 0, args[1], args[2]);
+ tcg_out_opc_reg(s, OPC_MFHI, args[0], 0, 0);
+ break;
case INDEX_op_div_i32:
tcg_out_opc_reg(s, OPC_DIV, 0, args[1], args[2]);
tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);
@@ -1602,6 +1610,8 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
{ INDEX_op_muls2_i32, { "r", "r", "rZ", "rZ" } },
{ INDEX_op_mulu2_i32, { "r", "r", "rZ", "rZ" } },
+ { INDEX_op_mulsh_i32, { "r", "rZ", "rZ" } },
+ { INDEX_op_muluh_i32, { "r", "rZ", "rZ" } },
{ INDEX_op_div_i32, { "r", "rZ", "rZ" } },
{ INDEX_op_divu_i32, { "r", "rZ", "rZ" } },
{ INDEX_op_rem_i32, { "r", "rZ", "rZ" } },
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 6cb7c2f..7ef79e0 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -89,8 +89,8 @@ typedef enum {
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_muls2_i32 1
-#define TCG_TARGET_HAS_muluh_i32 0
-#define TCG_TARGET_HAS_mulsh_i32 0
+#define TCG_TARGET_HAS_muluh_i32 1
+#define TCG_TARGET_HAS_mulsh_i32 1
/* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */
#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
--
1.8.1.4
- [Qemu-devel] [PULL 00/29] Three tcg patch sets, Richard Henderson, 2013/09/02
- [Qemu-devel] [PULL 01/29] tcg: Add muluh and mulsh opcodes, Richard Henderson, 2013/09/02
- [Qemu-devel] [PULL 02/29] tcg-mips: Implement mulsh, muluh,
Richard Henderson <=
- [Qemu-devel] [PULL 03/29] tcg-ppc64: Implement muluh, mulsh, Richard Henderson, 2013/09/02
- [Qemu-devel] [PULL 04/29] tcg: Constant fold div, rem, Richard Henderson, 2013/09/02
- [Qemu-devel] [PULL 05/29] qtest: Fix FMT_timeval vs time_t, Richard Henderson, 2013/09/02
- [Qemu-devel] [PULL 06/29] tcg: Change flush_icache_range arguments to uintptr_t, Richard Henderson, 2013/09/02
- [Qemu-devel] [PULL 07/29] tcg: Change tcg_qemu_tb_exec return to uintptr_t, Richard Henderson, 2013/09/02
- [Qemu-devel] [PULL 08/29] tcg: Fix next_tb type in cpu_exec, Richard Henderson, 2013/09/02
- [Qemu-devel] [PULL 09/29] tcg: Allow TCG_TARGET_REG_BITS to be specified independantly, Richard Henderson, 2013/09/02
- [Qemu-devel] [PULL 10/29] tcg: Define TCG_TYPE_PTR properly, Richard Henderson, 2013/09/02
- [Qemu-devel] [PULL 11/29] tcg: Define TCG_ptr properly, Richard Henderson, 2013/09/02
- [Qemu-devel] [PULL 12/29] tcg: Change frame pointer offsets to intptr_t, Richard Henderson, 2013/09/02