[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [PATCH RFC 3/3] hw/pci-host: catch acesses to unassigne

From: Michael S. Tsirkin
Subject: Re: [Qemu-devel] [PATCH RFC 3/3] hw/pci-host: catch acesses to unassigned pci addresses
Date: Mon, 2 Sep 2013 19:00:13 +0300

On Mon, Sep 02, 2013 at 04:53:50PM +0100, Peter Maydell wrote:
> On 2 September 2013 16:42, Marcel Apfelbaum <address@hidden> wrote:
> > On Mon, 2013-09-02 at 15:39 +0100, Peter Maydell wrote:
> >> This is happening at the wrong layer -- you want this memory
> >> region to be created and managed in the PCI core code so that
> >> we get correct PCI-spec behaviour for all our PCI controllers,
> >> not just the two x86 ones you've changed here.pci_address_space
> > I saw that the memory regions are part of the Host state and
> > duplicated for each host type(like pci_address_space).
> > Question, why are not pci_address_space and pci_hole present
> > in a core layer?
> >
> > I followed the existing code; from what you are saying
> > I understand that also the existing memory regions
> > like the one mentioned above should be moved in
> > the core layer, right?
> Ideally, yes, I think so. However that's not particularly
> a requirement for the changes you're trying to make here:
> at the moment what happens is that the pci controller
> creates the PCI memory and io memory regions (or cheats
> by reusing the system memory space[*]), passes them to
> the PCI core code (via pci_bus_new) and then they're
> the PCI code's responsibility to manage. So in the PCI
> code you can ignore where they came from when you're
> deciding how to manage these containers (and in this case
> what you do is just create your default region and map
> it in to the container at a suitable priority).
> [*] I'm pretty sure this is a bug in all platforms that do it.
> -- PMM

Well as usual this cheat originated with PIIX.
AFAIK PIIX actually has a shared bus for memory and PCI
so this is not a bug there, I think.


reply via email to

[Prev in Thread] Current Thread [Next in Thread]