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[Qemu-devel] [RFC 10/14] tcg-aarch64: Support div, mulu2
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [RFC 10/14] tcg-aarch64: Support div, mulu2 |
Date: |
Mon, 12 Aug 2013 11:44:51 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/aarch64/tcg-target.c | 42 ++++++++++++++++++++++++++++++++++++++++++
tcg/aarch64/tcg-target.h | 6 +++---
2 files changed, 45 insertions(+), 3 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 967526b..920c63c 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -276,6 +276,9 @@ typedef enum {
INSN_ASRV = 0x1ac02800,
INSN_RORV = 0x1ac02c00,
INSN_MUL = 0x1b007c00, /* MADD alias with Ra = xzr */
+ INSN_UMULH = 0x9bc07c00,
+ INSN_UDIV = 0x1ac00800,
+ INSN_SDIV = 0x1ac00c00,
/* Bitfield instructions */
INSN_BFM = 0x33000000,
@@ -1285,6 +1288,26 @@ static inline void tcg_out_addsub2(TCGContext *s,
AArch64Ext ext, TCGReg rl,
}
}
+static inline void tcg_out_mulu2(TCGContext *s, TCGReg rl, TCGReg rh,
+ TCGReg a, TCGReg b)
+{
+ if (rl == a || rl == b) {
+ if (rh == a || rh == b) {
+ /* Overlap on both outputs -- use a temporary. */
+ tcg_out_data2(s, INSN_MUL, E64, TCG_REG_TMP, a, b);
+ tcg_out_data2(s, INSN_UMULH, E64, rh, a, b);
+ tcg_out_mov(s, TCG_TYPE_I64, rl, TCG_REG_TMP);
+ } else {
+ /* Overlap on low output -- do high part first. */
+ tcg_out_data2(s, INSN_UMULH, E64, rh, a, b);
+ tcg_out_data2(s, INSN_MUL, E64, rl, a, b);
+ }
+ } else {
+ tcg_out_data2(s, INSN_MUL, E64, rl, a, b);
+ tcg_out_data2(s, INSN_UMULH, E64, rh, a, b);
+ }
+}
+
static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args, const int *const_args)
{
@@ -1453,6 +1476,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_mul_i32:
tcg_out_data2(s, INSN_MUL, ext, args[0], args[1], args[2]);
break;
+ case INDEX_op_div_i64:
+ ext = E64; /* fall through */
+ case INDEX_op_div_i32:
+ tcg_out_data2(s, INSN_SDIV, ext, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_divu_i64:
+ ext = E64; /* fall through */
+ case INDEX_op_divu_i32:
+ tcg_out_data2(s, INSN_UDIV, ext, args[0], args[1], args[2]);
+ break;
case INDEX_op_shl_i64:
ext = E64; /* fall through */
@@ -1620,6 +1653,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
REG0(5), const_args[4], true);
break;
+ case INDEX_op_mulu2_i64:
+ tcg_out_mulu2(s, args[0], args[1], args[2], args[3]);
+ break;
+
default:
tcg_abort(); /* opcode not implemented */
}
@@ -1666,6 +1703,10 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_sub_i64, { "r", "rZ", "rI" } },
{ INDEX_op_mul_i32, { "r", "r", "r" } },
{ INDEX_op_mul_i64, { "r", "r", "r" } },
+ { INDEX_op_div_i32, { "r", "r", "r" } },
+ { INDEX_op_div_i64, { "r", "r", "r" } },
+ { INDEX_op_divu_i32, { "r", "r", "r" } },
+ { INDEX_op_divu_i64, { "r", "r", "r" } },
{ INDEX_op_and_i32, { "r", "r", "rK" } },
{ INDEX_op_and_i64, { "r", "r", "rL" } },
{ INDEX_op_or_i32, { "r", "r", "rK" } },
@@ -1740,6 +1781,7 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_add2_i64, { "r", "r", "rZ", "rZ", "rAN", "rZ" } },
{ INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rAN", "rZ" } },
{ INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rAN", "rZ" } },
+ { INDEX_op_mulu2_i64, { "r", "r", "r", "r" } },
{ -1 },
};
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 0c71048..507e192 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -39,7 +39,7 @@ typedef enum {
#define TCG_TARGET_CALL_STACK_OFFSET 0
/* optional instructions */
-#define TCG_TARGET_HAS_div_i32 0
+#define TCG_TARGET_HAS_div_i32 1
#define TCG_TARGET_HAS_rem_i32 0
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
@@ -62,7 +62,7 @@ typedef enum {
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
-#define TCG_TARGET_HAS_div_i64 0
+#define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 0
#define TCG_TARGET_HAS_ext8s_i64 1
#define TCG_TARGET_HAS_ext16s_i64 1
@@ -85,7 +85,7 @@ typedef enum {
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
-#define TCG_TARGET_HAS_mulu2_i64 0
+#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muls2_i64 0
enum {
--
1.8.3.1
- [Qemu-devel] [RFC 00/14] tcg aarch64 improvements, Richard Henderson, 2013/08/12
- [Qemu-devel] [RFC 01/14] tcg-aarch64: Allow immediate operands to add and sub, Richard Henderson, 2013/08/12
- [Qemu-devel] [RFC 03/14] tcg-aarch64: Allow immediate operands to compare, Richard Henderson, 2013/08/12
- [Qemu-devel] [RFC 04/14] tcg-aarch64: Convert from opcode enums to insn enums, Richard Henderson, 2013/08/12
- [Qemu-devel] [RFC 05/14] tcg-aarch64: Support andc, orc, eqv, not, Richard Henderson, 2013/08/12
- [Qemu-devel] [RFC 06/14] tcg-aarch64: Handle zero as first argument to sub, Richard Henderson, 2013/08/12
- [Qemu-devel] [RFC 07/14] tcg-aarch64: Support movcond, Richard Henderson, 2013/08/12
- [Qemu-devel] [RFC 08/14] tcg-aarch64: Support deposit, Richard Henderson, 2013/08/12
- [Qemu-devel] [RFC 09/14] tcg-aarch64: Support add2, sub2, Richard Henderson, 2013/08/12
- [Qemu-devel] [RFC 10/14] tcg-aarch64: Support div, mulu2,
Richard Henderson <=
- [Qemu-devel] [RFC 11/14] tcg-aarch64: Improve tcg_out_movi, Richard Henderson, 2013/08/12
- [Qemu-devel] [RFC 12/14] tcg-aarch64: Avoid add with zero in tlb load, Richard Henderson, 2013/08/12
- [Qemu-devel] [RFC 13/14] tcg-aarch64: Use adrp in tcg_out_movi, Richard Henderson, 2013/08/12
- [Qemu-devel] [RFC 14/14] tcg-aarch64: Pass return address to load/store helpers directly., Richard Henderson, 2013/08/12
- [Qemu-devel] [RFC 02/14] tcg-aarch64: Allow immediate operands to and, or, xor, Richard Henderson, 2013/08/12