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Re: [Qemu-devel] [Patch] ARM: Add an L2 cache controller to KZM


From: peter
Subject: Re: [Qemu-devel] [Patch] ARM: Add an L2 cache controller to KZM
Date: Tue, 06 Aug 2013 10:00:41 +1000
User-agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (Gojō) APEL/10.8 EasyPG/1.0.0 Emacs/23.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO)

>>>>> "Andreas" == Andreas Färber <address@hidden> writes:

Andreas> Am 05.08.2013 11:18, schrieb Peter Maydell:
>> On 5 August 2013 02:21, Peter Chubb <address@hidden>
>> wrote:
>>> Reads to unassigned memory now return non-zero (since patch
>>> 9b8c69243585). This breaks guests runnong on i.MX31 that use the
>>> cache controller --- they poll forever waiting for the L2CC cache
>>> invalidate regsiter to be zero.
>> 
Andreas> Peter Ch., if you know the exact differences, why don't you
Andreas> just derive an imx-l2cc type (or so) derived from ARM's type,
Andreas> overriding the values mentioned above? Sounds trivial to me.

Because I don't know how -- can you point me at some documentation?

Peter C



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