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[Qemu-devel] [PULL 1/7] char/cadence_uart: Fix reset for unattached inst
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 1/7] char/cadence_uart: Fix reset for unattached instances |
Date: |
Mon, 15 Jul 2013 17:01:29 +0100 |
From: Peter Crosthwaite <address@hidden>
commit 1db8b5efe0c2b5000e50691eea61264a615f43de introduced an issue
where QEMU would segfault if you have an unattached Cadence UART.
Fix by guarding the flush-on-reset logic on there being a qemu_chr
attachment.
Reported-by: Soren Brinkmann <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Tested-by: Soren Brinkmann <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/char/cadence_uart.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index 131370a..4d457f8 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -157,7 +157,9 @@ static void uart_rx_reset(UartState *s)
{
s->rx_wpos = 0;
s->rx_count = 0;
- qemu_chr_accept_input(s->chr);
+ if (s->chr) {
+ qemu_chr_accept_input(s->chr);
+ }
s->r[R_SR] |= UART_SR_INTR_REMPTY;
s->r[R_SR] &= ~UART_SR_INTR_RFUL;
--
1.7.9.5
- [Qemu-devel] [PULL 0/7] arm-devs queue, Peter Maydell, 2013/07/15
- [Qemu-devel] [PULL 2/7] hw/cpu/a15mpcore: Correct default value for num-irq, Peter Maydell, 2013/07/15
- [Qemu-devel] [PULL 1/7] char/cadence_uart: Fix reset for unattached instances,
Peter Maydell <=
- [Qemu-devel] [PULL 7/7] ARM/highbank: add support for Calxeda ECX-2000 / Midway, Peter Maydell, 2013/07/15
- [Qemu-devel] [PULL 6/7] ARM/highbank: prepare for adding similar machines, Peter Maydell, 2013/07/15
- [Qemu-devel] [PULL 3/7] sd/pl181.c: Avoid undefined shift behaviour in RWORD macro, Peter Maydell, 2013/07/15
- [Qemu-devel] [PULL 4/7] hw/dma/omap_dma: Fix bugs with DMA requests above 32, Peter Maydell, 2013/07/15
- [Qemu-devel] [PULL 5/7] hw/arm/vexpress: Add alias for flash at address 0 on A15 board, Peter Maydell, 2013/07/15