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[Qemu-devel] RFC: Busifiying NAND

From: Peter Crosthwaite
Subject: [Qemu-devel] RFC: Busifiying NAND
Date: Wed, 26 Jun 2013 10:57:44 +1000

Hi All,

NAND emulation is a little strange, in that is doesnt have an
appropriate bus type (NAND was formerly SYS_BUS_DEVICE which was
completely wrong - so changed to DEVICE). Do want TYPE_NAND_BUS so
centrally support multiple NAND chips connected to the one NAND
interface? Currently controllers have to do this ad-hoc.

It occurs to me that theres possibly a lot in common with
TYPE_SSI_BUS. Main difference is it's parallel instead of series,
which at the end of the day, QEMU really shouldn't care about.

So proposed action Items:

Convert write-protect and chip select pins to GPIO - Supports
(awkward) case where CS/WP is managed by something other than the NAND
Generalise SSI (Syncrhonous Serial Interface) to SI (Synchronous Interface)
Inherit SSI from SI (trivially)
Inherit NAND_BUS from SI
Add support for Address/Command Latch Enable ALE/CLE to NAND_BUS
Convert NAND and controllers.

The trafficking of data to/from multiple devs is handled by generic SI
layer, while the NAND specifics are in the inherited bus layer.


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