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[Qemu-devel] [target-mips] How to use smp?


From: Dongxue Zhang
Subject: [Qemu-devel] [target-mips] How to use smp?
Date: Mon, 24 Jun 2013 15:52:52 +0800

Hello everybody, i want to use mips target with smp support.  When use 
command without smp, then the log stopped at "kernel panic", when -smp 2
added, it stoppted at "NR_IRQS:256".

I use the git qemu at 576156ffed72ab4feb0b752979db86ff8759a2a1
qemu configed with "./configure --target-list=mips64el-softmmu"
qemu run command "qemu-system-mips64el -kernel linux-3.8.2/vmlinux -nographic -smp 2"

The linux kernel used release version.


qemu-system-mips64el -kernel linux-3.8.2/vmlinux -nographic -smp 2 
QEMU 1.5.50 monitor - type 'help' for more information
(qemu) 
Linux version 3.8.2 (address@hidden) (gcc version 4.7.2 (GCC) ) #1 SMP Mon Jun 24 15:35:20 CST 2013
Config serial console: console=ttyS0,38400n8r
bootconsole [early0] enabled
CPU revision is: 000182a0 (MIPS 20Kc)
FPU revision is: 000f8200
Checking for the multiply/shift bug... no.
Checking for the daddiu bug... no.
Determined physical RAM map:
 memory: 0000000000001000 @ 0000000000000000 (reserved)
 memory: 00000000000ef000 @ 0000000000001000 (ROM data)
 memory: 0000000000be1000 @ 00000000000f0000 (reserved)
 memory: 000000000732f000 @ 0000000000cd1000 (usable)
Wasting 183736 bytes for tracking 3281 unused pages
Zone ranges:
  DMA      [mem 0x00000000-0x00ffffff]
  Normal   [mem 0x01000000-0x07ffffff]
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x00000000-0x07ffffff]
Primary instruction cache 32kB, VIVT, 4-way, linesize 32 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
PERCPU: Embedded 10 pages/cpu @98000000011c3000 s10816 r8192 d21952 u40960
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 32320
Kernel command line:  console=ttyS0,38400n8r
PID hash table entries: 512 (order: 0, 4096 bytes)
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
__ex_table already sorted, skipping sort
Enable cache parity protection for MIPS 20KC/25KF CPUs.
Memory: 115900k/117948k available (8466k kernel code, 2048k reserved, 3014k data, 356k init, 0k highmem)
Hierarchical RCU implementation.
        CONFIG_RCU_FANOUT set to non-default value of 32
        RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1.
NR_IRQS:256


Is there anyone have ideas to solve this problem?

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