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[Qemu-devel] [PATCH v2 5/5] intc/xilinx_intc: Dont lower IRQ when HIE cl


From: peter . crosthwaite
Subject: [Qemu-devel] [PATCH v2 5/5] intc/xilinx_intc: Dont lower IRQ when HIE cleared
Date: Tue, 11 Jun 2013 11:00:40 +1000

From: Peter Crosthwaite <address@hidden>

This is a little strange. It is lowering the parent IRQ pin on input
when HIE is cleared. There is no such behaviour in the real hardware.

ISR changes based on interrupt pin state are already guarded on HIE
being set. So we can just delete this if in its entirety.

Signed-off-by: Peter Crosthwaite <address@hidden>
---

 hw/intc/xilinx_intc.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index e9121cd..f343ee0 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -147,11 +147,6 @@ static void irq_handler(void *opaque, int irq, int level)
 {
     struct xlx_pic *p = opaque;
 
-    if (!(p->regs[R_MER] & 2)) {
-        qemu_irq_lower(p->parent_irq);
-        return;
-    }
-
     /* edge triggered interrupt */
     if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
         p->regs[R_ISR] |= (level << irq);
-- 
1.8.3.rc1.44.gb387c77.dirty




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