Re: [Qemu-devel] [PATCH v2 2/5] pci: store PCI hole ranges in guestinfo structure

[Michael S. Tsirkin]

On Thu, May 30, 2013 at 02:32:01PM +0200, Gerd Hoffmann wrote:
> On 05/30/13 14:19, Michael S. Tsirkin wrote:
> > On Thu, May 30, 2013 at 02:16:13PM +0200, Gerd Hoffmann wrote:
> >>   Hi,
> >>
> >>> +    } else {
> >>> +        guest_info->pci_info.w64.begin = 0x100000000ULL + 
> >>> above_4g_mem_size;
> >>> +        guest_info->pci_info.w64.end =  guest_info->pci_info.w64.begin +
> >>> +            (0x1ULL << 62);
> >>
> >> Doesn't this give unaligned windows?
> > 
> > PCI Bridge windows do not need to be size aligned.
> > 
> > In any case, the windows are *exactly* as calculated
> > by seabios - apparently it does not size-align windows either.
> 
> Surely not.  SeaBIOS sizes the 64bit window according to the space
> needed by the 64bit bars it wants to map there.

Ah, it's 64 bit. True. That's a seabios bug by the way:
if we add more devices by hotplug later, we want more
pci memory.

> >>> +    /* Set PCI window size the way seabios has always done it. */
> >>> +    /* TODO: consider just starting at below_4g_mem_size */
> >>
> >> Used to be that way.  Was changed for alignment reasons (i.e. 1G window
> >> starts at 1G border etc).
> > 
> > Where's the alignment requirement coming from?
> 
> seabios creates a mtrr entry for the window, which doesn't work in case
> it isn't aligned (at least not with a single entry).
> 
> Also real hardware tends to do it this way.
> 
> cheers,
>   Gerd

I see. I'll figure out the details and add a comment to this end.

But that's for the 32 bit window - I don't see it playing
with mtrrs for the 64 bit ranges.
So I'm guessing alignment isn't needed there, right?

-- 
MST