[Qemu-devel] Qemu for ARM and MRS/MSR banked registers instructions

[François Legal]

Hello,

Did anybody pointed out that there may be problems with Qemu decoding these 
MRS/MSR banked registers ?
In my code, I do several
mrs     %r0, sp_usr
mrs     %r0, lr_usr

from SVC mode or IRQ mode, and the result I get is CPSR in r0

I took a look in Qemu -> translate.c and op_helper.c, and it seem there is a 
function to access usr/fiq banked registers (get_user_reg) but the call 
hierarchy for this function is not very clear.

About the same goes for MSR banked registers.

Is it a known limitation or am I make mistakes in my code ?

Thanks

François