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Re: [Qemu-devel] [PATCH 01/10] target-ppc: optimize fabs, fnabs, fneg
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [PATCH 01/10] target-ppc: optimize fabs, fnabs, fneg |
Date: |
Mon, 15 Apr 2013 08:16:55 +0200 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Sat, Apr 13, 2013 at 02:20:10PM +0100, Peter Maydell wrote:
> On 13 April 2013 13:47, Aurelien Jarno <address@hidden> wrote:
> > fabs, fnabs and fneg are just flipping the bit sign of an FP register,
> > this can be implemented in TCG instead of using softfloat.
> > + tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
> > + ~(1LL << 63));
>
> "1LL << 63" is undefined behaviour; you probably want "1ULL << 63".
>
Thanks, I'll fix that in the next version.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
address@hidden http://www.aurel32.net
- [Qemu-devel] [PATCH 05/10] target-ppc: emulate prtyw and prtyd instructions, (continued)
- [Qemu-devel] [PATCH 05/10] target-ppc: emulate prtyw and prtyd instructions, Aurelien Jarno, 2013/04/13
- [Qemu-devel] [PATCH 09/10] target-ppc: emulate store doubleword pair instructions, Aurelien Jarno, 2013/04/13
- [Qemu-devel] [PATCH 07/10] target-ppc: emulate lfiwax instruction, Aurelien Jarno, 2013/04/13
- [Qemu-devel] [PATCH 04/10] target-ppc: emulate cmpb instruction, Aurelien Jarno, 2013/04/13
- [Qemu-devel] [PATCH 01/10] target-ppc: optimize fabs, fnabs, fneg, Aurelien Jarno, 2013/04/13
- [Qemu-devel] [PATCH 10/10] target-ppc: add support for extended mtfsf/mtfsfi forms, Aurelien Jarno, 2013/04/13
- Re: [Qemu-devel] [PATCH 00/10] target-ppc: emulate Power ISA 2.05 instructions, Alexander Graf, 2013/04/19