[Qemu-devel] [PATCH arm-devs v1 06/15] xilinx_spips: Fix QSPI FIFO size

[Peter Crosthwaite]

QSPI has a bigger FIFO than the regular SPI controller. Differentiate
between the two with correct FIFO sizes for each.

Signed-off-by: Peter Crosthwaite <address@hidden>
---

 hw/xilinx_spips.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c
index 06c2ec5..78a3fec 100644
--- a/hw/xilinx_spips.c
+++ b/hw/xilinx_spips.c
@@ -106,6 +106,9 @@
 #define RXFF_A          32
 #define TXFF_A          32
 
+#define RXFF_A_Q          (64 * 4)
+#define TXFF_A_Q          (64 * 4)
+
 /* 16MB per linear region */
 #define LQSPI_ADDRESS_BITS 24
 /* Bite off 4k chunks at a time */
@@ -575,6 +578,10 @@ static void xilinx_qspips_realize(DeviceState *dev, Error 
**errp)
     s->num_txrx_bytes = 4;
 
     xilinx_spips_realize(dev, errp);
+    fifo8_destroy(&s->rx_fifo);
+    fifo8_destroy(&s->tx_fifo);
+    fifo8_create(&s->rx_fifo, RXFF_A_Q);
+    fifo8_create(&s->tx_fifo, TXFF_A_Q);
     memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi",
                           (1 << LQSPI_ADDRESS_BITS) * 2);
     sysbus_init_mmio(sbd, &s->mmlqspi);
-- 
1.7.0.4